tangxifan
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89a97d83bd
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[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
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tangxifan
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ac6268d9ae
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[Engine] Bug fix on compilation errors
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2021-09-29 16:24:36 -07:00 |
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tangxifan
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c5ae93f177
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[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
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2021-09-29 16:17:40 -07:00 |
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tangxifan
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5da8f1db73
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[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
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2021-09-28 23:27:47 -07:00 |
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tangxifan
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7723e00e6c
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[Engine] Adding the function that builds a shift register module for BL/WLs
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2021-09-28 22:49:24 -07:00 |
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tangxifan
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834bdd2b07
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[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
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2021-09-28 17:29:03 -07:00 |
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tangxifan
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afd03d7eb7
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[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
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2021-09-28 15:56:07 -07:00 |
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tangxifan
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0a2979d616
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[Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols
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2021-09-28 14:20:35 -07:00 |
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tangxifan
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4968f0d11f
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Merge branch 'master' into qlbank_sr
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2021-09-28 14:20:30 -07:00 |
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tangxifan
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7633951263
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Merge pull request #19 from RapidSilicon/phy_mem_bank
Patch QuickLogic Memory Bank with Flatten BL/WL Protocol and WLR signals
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2021-09-28 13:26:57 -07:00 |
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tangxifan
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80232fc459
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[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
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2021-09-28 12:36:36 -07:00 |
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tangxifan
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4c04c0fbd7
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[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
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2021-09-28 12:35:42 -07:00 |
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tangxifan
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2ce2fb269a
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[HDL] Added a different FF model which is designed to drive WLW only
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2021-09-28 12:35:13 -07:00 |
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tangxifan
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6469ee3048
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[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
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2021-09-28 12:21:54 -07:00 |
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tangxifan
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0d72e115ac
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[Engine] Bug fix for the undriven WLR nets in top-level modules
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2021-09-28 11:53:38 -07:00 |
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tangxifan
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4400dae108
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[Test] Bug fix in the wrong arch name
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2021-09-28 11:40:25 -07:00 |
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tangxifan
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4aed045cdd
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[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
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2021-09-28 11:34:20 -07:00 |
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tangxifan
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811c898173
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[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
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2021-09-28 11:29:45 -07:00 |
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tangxifan
|
dae3554fd4
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[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
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2021-09-28 11:27:49 -07:00 |
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tangxifan
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05c6f1889e
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Merge pull request #17 from RapidSilicon/phy_mem_bank
Support flatten BL/WL protocol for QuickLogic memory bank
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2021-09-27 11:57:00 -07:00 |
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tangxifan
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b0a97a7052
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[Doc] Update doc about WLR usage for QL memory bank
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2021-09-27 10:24:04 -07:00 |
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tangxifan
|
f9bceff33a
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[Doc] Update documentation for the flatten BL/WL protocols
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2021-09-25 20:44:45 -07:00 |
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tangxifan
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33e9b27cb8
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[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
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2021-09-25 20:22:27 -07:00 |
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tangxifan
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29c351f5a4
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[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
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2021-09-25 19:34:21 -07:00 |
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tangxifan
|
e06ac11630
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[Engine] Bug fix
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2021-09-25 19:21:16 -07:00 |
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tangxifan
|
3cf31f1565
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[Engine] Fixed bugs
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2021-09-25 18:22:55 -07:00 |
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tangxifan
|
a56d1f4fdb
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[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
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2021-09-25 17:49:15 -07:00 |
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tangxifan
|
386812777c
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[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
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2021-09-25 12:49:32 -07:00 |
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tangxifan
|
1a2a2a6e63
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[FPGA-Bitstream] Relax fabric bitstream address check
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2021-09-25 12:03:33 -07:00 |
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tangxifan
|
8b72447dad
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[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
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2021-09-24 18:07:07 -07:00 |
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tangxifan
|
a49e3fe57a
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[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
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2021-09-24 16:30:18 -07:00 |
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tangxifan
|
025ee67bc7
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[Engine] Clear up compiler warning in tileable rr_graph builder
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2021-09-24 15:20:43 -07:00 |
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tangxifan
|
5f7617b682
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[Engine] Clear up compiler warnings in circuit library
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2021-09-24 15:18:50 -07:00 |
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tangxifan
|
f735c10b84
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[Engine] Clear up compiler warnings
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2021-09-24 15:18:31 -07:00 |
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tangxifan
|
2de4a460a8
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[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
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2021-09-24 15:15:32 -07:00 |
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tangxifan
|
74ffc8578f
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[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
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2021-09-24 15:05:25 -07:00 |
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tangxifan
|
be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
|
18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
|
7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
|
8c281a22b0
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[Engine] Add check codes to validate circuit models for BL/WL protocols
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2021-09-23 14:39:16 -07:00 |
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tangxifan
|
6645b70ae3
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[Engine] Upgrade parser to support BL/WL protocols
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2021-09-23 14:25:25 -07:00 |
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tangxifan
|
d4e3445153
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[Engine] update internal data structure for new syntax in configuration protocol
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2021-09-22 17:32:45 -07:00 |
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tangxifan
|
1ca1b0f3e9
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[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
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2021-09-22 15:58:05 -07:00 |
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tangxifan
|
655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
|
a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
|
53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
|
3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
|
212c5bd642
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[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
|
182e9a7baf
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Merge pull request #15 from RapidSilicon/phy_mem_bank
Support multi-region for QL memory bank configuration protocol
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2021-09-22 14:37:17 -07:00 |
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tangxifan
|
b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |