tangxifan
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43c569b612
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[FPGA-Bitstream] Encapusulate the data structur storing memory bank fabric bitstream for flatten BL/WL into an object
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2021-09-30 14:47:21 -07:00 |
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tangxifan
|
4d8019b7c1
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[FPGA-Bitstream] Bug fix in bitstream generator for shift-register-based memory bank
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2021-09-29 22:32:45 -07:00 |
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tangxifan
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2d4c200d58
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[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
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2021-09-29 20:56:02 -07:00 |
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tangxifan
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f456c7e236
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[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
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2021-09-29 20:34:25 -07:00 |
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tangxifan
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b87b7a99c5
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[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
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tangxifan
|
8f0ae937bc
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[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
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2021-09-29 16:57:49 -07:00 |
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tangxifan
|
41cc375746
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[Arch] define default CCFF model in ql bank example architecture that uses shift registers
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2021-09-29 16:34:40 -07:00 |
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tangxifan
|
4926c323e7
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[Engine] Bug fix due to the optional syntax ``num_bank`` were required in XML
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2021-09-29 16:32:29 -07:00 |
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tangxifan
|
89a97d83bd
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[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
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tangxifan
|
ac6268d9ae
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[Engine] Bug fix on compilation errors
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2021-09-29 16:24:36 -07:00 |
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tangxifan
|
c5ae93f177
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[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
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2021-09-29 16:17:40 -07:00 |
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tangxifan
|
5da8f1db73
|
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
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2021-09-28 23:27:47 -07:00 |
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tangxifan
|
7723e00e6c
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[Engine] Adding the function that builds a shift register module for BL/WLs
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2021-09-28 22:49:24 -07:00 |
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tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
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2021-09-28 17:29:03 -07:00 |
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tangxifan
|
afd03d7eb7
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[Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers
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2021-09-28 15:56:07 -07:00 |
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tangxifan
|
0a2979d616
|
[Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols
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2021-09-28 14:20:35 -07:00 |
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tangxifan
|
4968f0d11f
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Merge branch 'master' into qlbank_sr
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2021-09-28 14:20:30 -07:00 |
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tangxifan
|
7633951263
|
Merge pull request #19 from RapidSilicon/phy_mem_bank
Patch QuickLogic Memory Bank with Flatten BL/WL Protocol and WLR signals
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2021-09-28 13:26:57 -07:00 |
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tangxifan
|
80232fc459
|
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
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2021-09-28 12:36:36 -07:00 |
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tangxifan
|
4c04c0fbd7
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[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
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2021-09-28 12:35:42 -07:00 |
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tangxifan
|
2ce2fb269a
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[HDL] Added a different FF model which is designed to drive WLW only
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2021-09-28 12:35:13 -07:00 |
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tangxifan
|
6469ee3048
|
[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
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2021-09-28 12:21:54 -07:00 |
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tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
|
2021-09-28 11:53:38 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
4aed045cdd
|
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
|
2021-09-28 11:34:20 -07:00 |
|
tangxifan
|
811c898173
|
[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
|
2021-09-28 11:29:45 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
|
2021-09-28 11:27:49 -07:00 |
|
tangxifan
|
05c6f1889e
|
Merge pull request #17 from RapidSilicon/phy_mem_bank
Support flatten BL/WL protocol for QuickLogic memory bank
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2021-09-27 11:57:00 -07:00 |
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tangxifan
|
b0a97a7052
|
[Doc] Update doc about WLR usage for QL memory bank
|
2021-09-27 10:24:04 -07:00 |
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tangxifan
|
f9bceff33a
|
[Doc] Update documentation for the flatten BL/WL protocols
|
2021-09-25 20:44:45 -07:00 |
|
tangxifan
|
33e9b27cb8
|
[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs
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2021-09-25 20:22:27 -07:00 |
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tangxifan
|
29c351f5a4
|
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
|
2021-09-25 19:34:21 -07:00 |
|
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
|
tangxifan
|
3cf31f1565
|
[Engine] Fixed bugs
|
2021-09-25 18:22:55 -07:00 |
|
tangxifan
|
a56d1f4fdb
|
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
|
2021-09-25 17:49:15 -07:00 |
|
tangxifan
|
386812777c
|
[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
|
2021-09-25 12:49:32 -07:00 |
|
tangxifan
|
1a2a2a6e63
|
[FPGA-Bitstream] Relax fabric bitstream address check
|
2021-09-25 12:03:33 -07:00 |
|
tangxifan
|
8b72447dad
|
[FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs
|
2021-09-24 18:07:07 -07:00 |
|
tangxifan
|
a49e3fe57a
|
[FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank
|
2021-09-24 16:30:18 -07:00 |
|
tangxifan
|
025ee67bc7
|
[Engine] Clear up compiler warning in tileable rr_graph builder
|
2021-09-24 15:20:43 -07:00 |
|
tangxifan
|
5f7617b682
|
[Engine] Clear up compiler warnings in circuit library
|
2021-09-24 15:18:50 -07:00 |
|
tangxifan
|
f735c10b84
|
[Engine] Clear up compiler warnings
|
2021-09-24 15:18:31 -07:00 |
|
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
|
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
|
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
|
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
|
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
|
tangxifan
|
8c281a22b0
|
[Engine] Add check codes to validate circuit models for BL/WL protocols
|
2021-09-23 14:39:16 -07:00 |
|
tangxifan
|
6645b70ae3
|
[Engine] Upgrade parser to support BL/WL protocols
|
2021-09-23 14:25:25 -07:00 |
|
tangxifan
|
d4e3445153
|
[Engine] update internal data structure for new syntax in configuration protocol
|
2021-09-22 17:32:45 -07:00 |