Commit Graph

1560 Commits

Author SHA1 Message Date
tangxifan e48de682ed [core] fixed som ebugs 2023-11-03 14:39:28 -07:00
tangxifan b2e1eb30c7 [core] code format 2023-11-03 13:50:04 -07:00
tangxifan 21813eb59f [core] now full testbench uses bitstream in different sizes 2023-11-03 13:48:21 -07:00
tangxifan 2cd3453629 [core] fixed the bug in ccff v2 on config enable signal drivers 2023-11-03 10:25:12 -07:00
tangxifan 8bee65853c [core] add missing files 2023-11-02 19:01:25 -07:00
tangxifan 649d44b2d8 [core] code format 2023-11-02 16:33:55 -07:00
tangxifan 36fa020c15 [core] syntax 2023-11-02 16:33:19 -07:00
tangxifan 75e9e98e5d [core] add two new commands to output testbench parts 2023-11-02 16:06:48 -07:00
tangxifan 3d4f1505b6 [core] code format 2023-10-20 22:02:56 -07:00
tangxifan 66c3226fad [core] now follow module unique index when naming grouped configuration memories 2023-10-20 22:01:19 -07:00
tangxifan e4b204f2e4 [core] code format 2023-10-20 21:14:07 -07:00
tangxifan 76a4b8a82b [core] remove the prefix of grouped memory blocks 2023-10-20 21:13:37 -07:00
tangxifan 5bae2bf54d [core] code format 2023-10-19 23:05:49 -07:00
tangxifan 4b00651a46 [core] now name indexing is applied to netlist names 2023-10-19 23:03:48 -07:00
tangxifan 7ba6795fe2 [core] fixed a bug 2023-10-06 18:50:26 -07:00
tangxifan 83ef35b2da [core] fixed a bug 2023-10-06 18:47:20 -07:00
tangxifan 3440768840 [core] code format 2023-10-06 18:37:54 -07:00
tangxifan e102c9bddc [core] fixed a bug 2023-10-06 18:37:28 -07:00
tangxifan 93cbbf2045 [core] code format 2023-10-06 18:20:55 -07:00
tangxifan b07111497c [core] enable options in xml writers 2023-10-06 18:20:17 -07:00
tangxifan ae63c9d441 [core] code format 2023-10-06 17:28:25 -07:00
tangxifan 1e8bf1cece [core] deploy options 2023-10-06 17:28:02 -07:00
tangxifan f30663f708 [core] code format 2023-10-06 14:08:09 -07:00
tangxifan 108bbad8d4 [core] syntax 2023-10-06 14:07:44 -07:00
tangxifan 80856f1b70 [core] adding new options and rewrite options for bitfile writer 2023-10-06 13:54:29 -07:00
tangxifan a15db83267 [core] code format 2023-09-26 11:41:11 -07:00
tangxifan ea91182216 [core] check option conflicts 2023-09-26 11:40:42 -07:00
tangxifan c4bce834e4 [core] code format 2023-09-25 22:34:39 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 1624dc9764 [core] code format 2023-09-25 21:13:50 -07:00
tangxifan 76f446caec [core] fixed a bug 2023-09-25 21:13:11 -07:00
tangxifan dbd466cdec [core] now support tile port merge 2023-09-25 18:16:24 -07:00
tangxifan 3adf81046a [core] code format 2023-09-25 17:22:26 -07:00
tangxifan 5e269e8bc4 [core] support port merging at grid modules 2023-09-25 17:21:58 -07:00
tangxifan edb0e687f1 [core] code format 2023-09-23 12:15:53 -07:00
tangxifan 11de8965a8 [core] fixed some bugs 2023-09-23 12:15:31 -07:00
tangxifan 860cfd53c6 [core] fixed critical bugs in renaming modules 2023-09-23 11:51:31 -07:00
tangxifan ca3617a029 [core] code format 2023-09-20 20:37:27 -07:00
tangxifan 1ef38b6a64 [core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming 2023-09-20 20:34:21 -07:00
tangxifan c105b56bf0 [core] code format 2023-09-18 23:31:27 -07:00
tangxifan 43fd08a3fe [core] fixed a bug 2023-09-18 23:31:09 -07:00
tangxifan 4d11f73471 [core] fixed a bug 2023-09-18 20:43:15 -07:00
tangxifan a1e609c901 [core] fixed some bugs 2023-09-18 16:39:07 -07:00
tangxifan 1daabb990e [core] code format 2023-09-18 15:35:13 -07:00
tangxifan 110301a2e4 [core] now tile port naming can follow index 2023-09-18 15:34:40 -07:00
tangxifan e46e58527a [core] code format 2023-09-17 23:16:38 -07:00
tangxifan eeb1bd6662 [core] fixed some bugs 2023-09-17 23:16:15 -07:00
tangxifan c6175aa514 [core] code format 2023-09-17 22:37:48 -07:00
tangxifan ef97127c63 [core] fixed some bugs in testbenches when renaming top modules 2023-09-17 22:34:00 -07:00
tangxifan c14277a674 [core] fixing bugs 2023-09-17 17:57:57 -07:00
tangxifan d5152dc16d [core] fixed a bug on the hierarchy writer 2023-09-17 17:42:25 -07:00
tangxifan 4ccb4737be [core] code format 2023-09-17 17:33:10 -07:00
tangxifan f79da76656 [core] supporting renaming on all the verilog modules 2023-09-17 17:29:11 -07:00
tangxifan 72a3c05747 [core] code format 2023-09-17 13:29:30 -07:00
tangxifan ccd4c1861b [core] developing new command to write module naming rules 2023-09-16 19:37:06 -07:00
tangxifan 32df673d72 [core] code format 2023-09-16 18:35:33 -07:00
tangxifan 200ecad74a [core] fixed bugs in bitgen 2023-09-16 18:34:55 -07:00
tangxifan 058bb1ef51 [core] code format 2023-09-16 18:24:38 -07:00
tangxifan 6fc2924438 [core] syntax 2023-09-16 18:16:30 -07:00
tangxifan d61d88f12e [core] fixed some bugs in verilog writer due to renaming 2023-09-16 18:13:22 -07:00
tangxifan 37573abc22 [core] code format 2023-09-15 23:32:40 -07:00
tangxifan c85c64eb5a [core] syntax 2023-09-15 23:30:34 -07:00
tangxifan bc407e5d69 [core] code complete for rename modules 2023-09-15 23:22:31 -07:00
tangxifan 2a45b49890 [core] developing renaming commands. options and functions 2023-09-15 19:15:18 -07:00
tangxifan af67b02cca [lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules 2023-09-15 13:51:14 -07:00
tangxifan eaadff3448 [core] fixed some bugs 2023-09-06 22:49:56 -07:00
tangxifan bcb82d43af [core] code format 2023-09-06 22:40:59 -07:00
tangxifan 2fee56548b [core] fixed some bugs 2023-09-06 22:39:59 -07:00
tangxifan f544953085 [core] code format 2023-09-06 22:29:30 -07:00
tangxifan f8b2eec988 [core] now default net type wire will not appear. timescale does not show in fabric netlists 2023-09-06 22:27:51 -07:00
tangxifan 539bcba851 [core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types 2023-09-06 17:23:41 -07:00
tangxifan dfe5447e2a [core] format 2023-08-25 15:21:24 -07:00
tangxifan b8c66b06a0 [core] syntax 2023-08-25 15:17:52 -07:00
tangxifan 717906ea17 [core] code format 2023-08-25 15:13:39 -07:00
tangxifan 89b392a51f [core] adapt changes in is_sb_exist() 2023-08-25 15:13:00 -07:00
tangxifan 55e5f738ce [core] code format 2023-08-25 11:58:15 -07:00
tangxifan 92f92658c9 [core] remove useless errors 2023-08-25 11:53:49 -07:00
tangxifan a6d43beaca [core] now tile verilog writer supports relative paths 2023-08-21 22:25:52 -07:00
tangxifan 66cc375996 [core] remove debugging messages 2023-08-18 22:08:47 -07:00
tangxifan 19d4d9a16d [core] code format 2023-08-18 21:05:26 -07:00
tangxifan fc523bed32 [core] fixed some bugs in spotting the correct pin index of given subtiles 2023-08-18 21:04:37 -07:00
tangxifan 3d8f76269a [core] fixed a bug when io is in the center of 3x3 fabric 2023-08-18 12:42:15 -07:00
tangxifan e9fd22790d [core] fixed a bug where pass thru cb blocks are not connected in tiles 2023-08-17 15:26:32 -07:00
tangxifan 399f087c50 [core] code format 2023-08-17 13:54:31 -07:00
tangxifan 414f7379c6 [core] fixed some bugs in debugging messages 2023-08-17 13:52:21 -07:00
chungshien aabbd330b3 Address follow up from PR 1259 (1) 2023-08-11 08:06:57 -07:00
chungshien 6c0df8da20 Address follow up from PR 1259 2023-08-11 07:59:53 -07:00
tangxifan 788e3c17a9 [core] format 2023-08-08 23:02:20 -07:00
tangxifan 1c8c4fedbb [core] fix memory leak 2023-08-08 23:01:52 -07:00
tangxifan ff6fa1e90c [core] fix memory leak 2023-08-08 22:41:43 -07:00
tangxifan 94d80a9b7c [core] code format 2023-08-08 16:28:56 -07:00
tangxifan 867da98d3f [core] update to use latest api from vpr upstream 2023-08-08 16:28:19 -07:00
tangxifan bb945b2816
Merge branch 'master' into openfpga-issue-1256 2023-08-07 13:49:19 -07:00
tangxifan 4d37421735 [core] fixed a bug on loading subkey to support fabric keys 2023-08-07 10:40:22 -07:00
tangxifan 18acb39fad [core] fixed a bug where heterogeneous fabric may fail 2023-08-06 22:12:32 -07:00
tangxifan 26c8b5146c [core] fixed a bug where release build will fail 2023-08-06 21:44:15 -07:00
tangxifan c5b1918e47 [core] fixed a critical bug which causes reg test failures when group_config_block is off 2023-08-06 13:11:17 -07:00
tangxifan beee2369c9 [core] fixed a bug 2023-08-05 22:06:17 -07:00
tangxifan a1f8b3c441 [core] fixed a bug on bitstream generator on supporting group_config_block 2023-08-05 21:58:03 -07:00
tangxifan 68f07d6fc9 [core] code format 2023-08-05 20:53:58 -07:00
tangxifan 2aab94cd6c [core] syntax 2023-08-05 14:11:57 -07:00
tangxifan 22816a7ed4 [core] syntax 2023-08-05 14:04:57 -07:00
tangxifan f4d7ad2bd1 [core] trying to fix the bug on instance naming so that bitstream generation can work 2023-08-05 13:38:51 -07:00
tangxifan 9a23dc7bff [core] fixed some bugs which causes architecture bitstream generation failed when supporting group_config_block 2023-08-04 21:20:21 -07:00
tangxifan 7d8d686f74 [core] add status codes to build grid modules 2023-08-04 16:52:43 -07:00
tangxifan bb9cf6dbcb [core] fixed a critical bug which causes undriven nets on config bus in group config block 2023-08-04 16:45:15 -07:00
tangxifan 64c0839e30 [core] now verilog writer supports memory group modules 2023-08-04 16:11:33 -07:00
tangxifan a0f81a5bf2 [core] now verilog generator can output feedthrough memory module to files 2023-08-04 13:34:38 -07:00
tangxifan 5bc8925c3a [core] fixed multiple bugs on fabric generator on supporting group_config_block 2023-08-04 12:36:59 -07:00
tangxifan 3c2518ac70 [core] adding debugging message when verbose is enabled 2023-08-04 11:20:05 -07:00
tangxifan 99bda2e5b0 [core] debugging 2023-08-03 22:50:14 -07:00
tangxifan 2aeeb0cacf [core] fixed a bug which causes reg tests failed 2023-08-03 22:13:27 -07:00
tangxifan d3895c3dc0 [core] code format 2023-08-03 17:34:25 -07:00
tangxifan f4cbc95053 [core] syntax 2023-08-03 17:33:57 -07:00
tangxifan 5618f1d567 [core] now bitgen uses config child types 2023-08-03 16:06:19 -07:00
tangxifan 3331540ed6 [core] using config child type in bitstream generation 2023-08-03 14:24:22 -07:00
tangxifan 2facde2097 [core] reworked fabric generator to use config child type 2023-08-03 12:57:50 -07:00
tangxifan 5895a1d96b [core] reworking fabric generator based on latest changes on configurable children 2023-08-02 22:50:19 -07:00
tangxifan 27cae41123 [core] rework physical and logical types of configurable child 2023-08-02 20:37:27 -07:00
tangxifan 87f2822ef8 [core] working on logical and physical children 2023-08-02 19:46:27 -07:00
tangxifan c05f12ac11 [core] sync up logical-to-physical configurable child mapping after physical memory build-up 2023-08-02 12:24:16 -07:00
tangxifan 470ab84489 [core] developing group config block support for routing module 2023-08-01 22:57:22 -07:00
tangxifan 53050b94ab [core] developing memory group modules in grid modules 2023-08-01 17:50:03 -07:00
chungshien eed96b395e Misc - update comment + remove code that not being used 2023-08-01 07:33:17 -07:00
tangxifan 23643f3fb1 [core] developing the physical memory block builder 2023-07-31 22:57:26 -07:00
tangxifan 2d2b8f67aa [core] adding new option '--group_config_block' to command 'build_fabric' 2023-07-31 17:32:48 -07:00
chungshien c1b5ca0941
Merge branch 'master' into openfpga-issue-1256 2023-07-31 01:18:10 -07:00
cschai aae037bf77 Address comment 2023-07-30 02:18:48 -07:00
cschai 838cf0d818 Address comment 2023-07-30 01:14:11 -07:00
cschai 56d76741d5 Address comment 2023-07-30 00:39:16 -07:00
cschai 63459218e5 Address comment 2023-07-30 00:24:40 -07:00
tangxifan beaa687a20 [core] fixed bugs on supporting heterogeneous blocks in tile modules 2023-07-27 20:29:18 -07:00
tangxifan c2066cc63c [core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules 2023-07-27 13:33:23 -07:00
tangxifan 156cb800aa [core] fixed a critical bug which causes wrong connections in tile modules 2023-07-27 12:22:16 -07:00
tangxifan dd486f5ccb [core] fixed a bug on checking if cb is in a tile 2023-07-27 11:14:05 -07:00
tangxifan cfec6c88f1 [core] fixed a bug in cb instance naming 2023-07-27 10:59:46 -07:00
tangxifan be0715a81c [core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules 2023-07-27 10:42:56 -07:00
tangxifan 97219fd825 [core] add more verbose to help debug failed test cases 2023-07-26 23:26:11 -07:00
tangxifan 19ed9ea669
Merge branch 'master' into openfpga-issue-1256 2023-07-26 10:32:30 -07:00
tangxifan f5e8f175fb [core] fixed a bug which causes flow failures when group_tile is not enabled 2023-07-25 21:27:58 -07:00
tangxifan 83428a209e [core] fixed a bug on io indexing which causes tile-based test cases failed in dv 2023-07-25 16:03:50 -07:00
tangxifan de6956530f [core] disable pnr sdc for tile-based fabric 2023-07-25 15:38:41 -07:00
tangxifan 6ecbbb3a94 [core] fixed a bug in fabric bitgen due to tile modules 2023-07-25 14:49:12 -07:00
tangxifan 95a32628ab [core] fixed the bug in arch bitgen due to the tile modules 2023-07-25 14:15:15 -07:00
tangxifan 64698443c9 [core] fixed a bug on io location map for tile modules 2023-07-24 22:11:57 -07:00
tangxifan 2105abdbca [core] fixed a bug 2023-07-24 21:26:29 -07:00
tangxifan e7d714b94d [core] fixed a bug on the tile module port addition: some grid output was not pulled out 2023-07-24 21:21:25 -07:00
tangxifan b8d080b08e [core] fixed a bug where undriven cb ports are not connected to tile 2023-07-24 20:40:25 -07:00
tangxifan 3745897ff6 [core] fixed a few bugs 2023-07-24 16:10:29 -07:00
tangxifan 48b0ba8b78 [core] format 2023-07-24 15:00:26 -07:00
tangxifan 4294914987 [core] fixed compiler warnings 2023-07-24 14:59:43 -07:00
tangxifan 812473ef04 [core] fixed the bug on io location map for tiled top module 2023-07-24 14:50:39 -07:00
tangxifan da36b735c6 [core] syntax 2023-07-24 12:13:45 -07:00
tangxifan f031148959 [core] syntax 2023-07-23 22:39:36 -07:00
tangxifan f551188d0f [core] developed tile directs to support tile modules 2023-07-23 21:45:45 -07:00
tangxifan 14666f3ae5 [core] sync 2023-07-23 20:45:59 -07:00
tangxifan 0b3b7b5472 [core] hotfix 2023-07-23 13:39:06 -07:00
tangxifan 1ee7448070 [core] supporting tile annotation (for global port) in tile modules 2023-07-23 13:38:16 -07:00
tangxifan 399259ea1d [core] adding prog clock arch support for tile modules 2023-07-23 13:11:13 -07:00
tangxifan 0f3f4b0d81 [core] now tile module use unique port name (for heterogeneous blocks) 2023-07-22 23:55:54 -07:00
tangxifan 003d9515ff [core] developing tile-based top module builder 2023-07-22 17:13:30 -07:00
tangxifan 93c5a68592 [core] developing top-level nets for tiles 2023-07-21 23:21:53 -07:00
Chung Shien Chai 6c03819c5f 100% limited new flow for flatten bl/wl protocol 2023-07-21 03:14:26 -07:00
tangxifan fcf308fcd6 [core] developing inter-tile connections for top module 2023-07-20 23:00:35 -07:00
Chung Shien Chai 39934f9d16 Address issue 1256 2023-07-20 22:34:18 -07:00
tangxifan b70f7fb1b6 [core] now option conflicts in command 'build_fabric' can error out 2023-07-20 21:22:07 -07:00
tangxifan 6b92299e39 [core] start working on the net build-up for tile instances under the top-level module 2023-07-20 17:38:13 -07:00
tangxifan 88c5d122ca [core] syntax 2023-07-20 17:12:10 -07:00
tangxifan db179ec4bb [core] split tile instance builder and the classic fine-grained builder 2023-07-20 17:07:07 -07:00
tangxifan ef214f4590 [core] code format 2023-07-20 17:00:29 -07:00
tangxifan 6458580e3e [core] move child instance builder to a separated source file as these codes are expanding in size 2023-07-20 16:59:39 -07:00
tangxifan bd265334b5 [core] added tile instances to top module builder 2023-07-19 23:26:55 -07:00
tangxifan a06b9a0f48 [core] now start to develop the tile instances under the top module 2023-07-19 22:22:07 -07:00
tangxifan 2e69eebea0 [core] now tile module builder is working 2023-07-19 17:23:44 -07:00
tangxifan 0d03d7b483 [core] now fabric tile cache both grid and gsb coord for pb 2023-07-19 17:20:53 -07:00
tangxifan 778d03610c [core] debugging 2023-07-19 15:27:05 -07:00
tangxifan 001b3b3f8b [core] debugging 2023-07-19 14:38:07 -07:00
tangxifan d03fa92ddf [core] debugging 2023-07-19 12:49:35 -07:00
tangxifan 48e207d3e4 [core] debugging 2023-07-19 12:22:57 -07:00
tangxifan 6607bb7e48 [core] now fpga verilog supports tile modules 2023-07-18 22:35:22 -07:00
tangxifan 5ae146bd86 [core] finish up tile module builder 2023-07-18 21:17:40 -07:00
tangxifan 0dcec9d8e5 [core] finishing up tile module builder 2023-07-18 17:56:27 -07:00
tangxifan 403ed4ea60 [core] still developing tile module port and net builder 2023-07-18 16:03:47 -07:00
tangxifan aabcc25567 [core] developing tile module port and net builder 2023-07-17 23:06:55 -07:00
tangxifan ba4b7e3522 [core] developing tile module builder 2023-07-16 15:18:09 -07:00
tangxifan 98c598cec2 [core] unique tile identifier done 2023-07-15 22:54:33 -07:00
tangxifan ea8d128789 [core] syntax 2023-07-15 20:29:21 -07:00
tangxifan c2ef5ca408 [core] developing top-left style tile info 2023-07-14 22:48:44 -07:00
tangxifan 091ac88c7e [lib] code format 2023-07-14 12:16:40 -07:00
tangxifan 3bc959dcec [lib] create tile config lib and start integration to core 2023-07-14 12:13:31 -07:00
tangxifan c58035dbd4 [core] start developing option --group_tile for build_fabric 2023-07-14 11:01:04 -07:00
tangxifan 3de4d3fc09 [core] add a new command 'write_fabric_key' and now writer supports module-level keys 2023-07-08 18:12:51 -07:00
tangxifan 433391eec4 [core] move new functions to a separated source file 2023-07-07 15:03:03 -07:00
tangxifan d3aa4c53d0 [core] now support rebuild configuarable children for ccff submodules 2023-07-07 14:51:21 -07:00
tangxifan a1b13b8e12 [core] overload submodule configurable children from fabric key 2023-07-06 22:47:57 -07:00
tangxifan d3109ee88b [core] developing configurable children reloading from fabric key 2023-07-06 21:53:22 -07:00
tangxifan ddfb0c4afd [core] now mock fpga top supports fpga core wrapper 2023-06-26 15:06:11 -07:00
tangxifan 83fa6a421e [core] code format 2023-06-26 10:06:17 -07:00
tangxifan 70f40cd21a [core] fixing bugs in the preconfig module when supporting dut module of fpga_core 2023-06-26 10:03:19 -07:00
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
tangxifan 205881d0e7 [core] fixed the bug when using fpga_core instead of fpga_top 2023-06-25 18:03:15 -07:00
tangxifan 150653287d [core] supporting io naming for verilog testbench generators 2023-06-25 15:29:27 -07:00
tangxifan 987a562e0f [core] fixed the bug when checking mapping status of fpga core ports 2023-06-23 17:21:52 -07:00
tangxifan 463332c77a [core] code complete for adding nets between top and core module 2023-06-23 13:21:25 -07:00
tangxifan b30148f8fb [core] apply more sanity checks on top module port 2023-06-23 12:37:46 -07:00
tangxifan 2484150ab6 [core] working on port addition to top module 2023-06-23 12:21:47 -07:00
tangxifan 8bd9ae02fd [core] io name map now supports dummy port direction 2023-06-23 11:09:33 -07:00
tangxifan 7961223eac [core] enabling io naming rules in fabric builder 2023-06-22 22:18:09 -07:00
tangxifan 61544af2b4 [core] start adding new options 2023-06-21 14:01:00 -07:00
tangxifan b2d1d1b6bd [core] fixed a bug on fpga bitstream when supporting fpga_core 2023-06-19 14:40:38 -07:00
tangxifan 299b42873d [core] fix no warning build 2023-06-19 13:01:43 -07:00
tangxifan a4f26798b0 [core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc 2023-06-19 11:59:48 -07:00
tangxifan 63ee0c980e [core] fixed some bugs 2023-06-18 22:12:54 -07:00
tangxifan d9499f2b40 [core] now fpga bitstream supports the wrapper module 2023-06-18 21:58:36 -07:00
tangxifan bdda695cc0 [core] format 2023-06-18 21:18:35 -07:00
tangxifan cef573529d [core] now fpga verilog can output fpga core netlist 2023-06-18 21:17:50 -07:00
tangxifan c7ade72200 [core] code complete for the core wrapper creator. Start debugging 2023-06-18 19:17:42 -07:00
tangxifan 8bc70b590a [core] developing fpga_core insertion 2023-06-17 23:42:45 -07:00
tangxifan ee59bdb675 [core] code format 2023-06-07 18:55:34 -07:00
tangxifan 327f7f4dab [core] now adapt to latest API of DeviceGrid 2023-06-07 18:54:48 -07:00
tangxifan b6c90eb99a [core] fixed several bugs which causes bgf and pcf support in mock wrapper failed 2023-05-27 12:13:16 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 0abc5af1a9 [core] fixed the bug supporting global nets 2023-05-26 20:44:04 -07:00
tangxifan a9e5e1af89 [core] now fabric netlist include mock wrapper 2023-05-26 18:49:57 -07:00
tangxifan 788b1495dd [core] split a big function to 4 sub functions so that we can efficiently reuse for mock wrapper 2023-05-26 17:31:07 -07:00
tangxifan f7afbfa0bd [core] fixed some bugs 2023-05-26 12:26:30 -07:00
tangxifan e9848c5728 [core] typo 2023-05-26 10:24:21 -07:00
tangxifan 45e25e4152 [core] hooking up API with command 2023-05-25 19:50:39 -07:00
tangxifan affe5c5d1e [core] developing mock wrapper generator 2023-05-25 18:50:47 -07:00
tangxifan ab263aa5b1 [core] code format 2023-05-25 15:02:03 -07:00
tangxifan 8d7429fc2b [core] adding the new command 'write_mock_fpga_wrapper' 2023-05-25 12:58:12 -07:00
tangxifan dab89322b3 [core] fixed the bug in I/O location map build-up when supporting subtiles 2023-05-04 09:51:05 +08:00
tangxifan cb0e6b9e17 [core] fixed a critical bug 2023-05-03 21:46:35 +08:00
tangxifan 6c48c57421 [core] fixed some bugs in the subtile support 2023-05-03 21:23:52 +08:00
tangxifan 7bedc965ac [core] supporting subtile 2023-05-03 17:30:58 +08:00
tangxifan 18b078d1d5 [core] fixed bugs which cause ci failed 2023-04-24 21:20:07 +08:00
tangxifan e11e4dc3f4 [core] comment on current limitations 2023-04-24 14:59:43 +08:00
tangxifan d9af8dd722 [core] did some dirty fix but now dv should pass. Not sure why usig a shorter bitstream does not work 2023-04-24 14:50:42 +08:00
tangxifan 679c6e9b43 [core] debugging 2023-04-24 14:05:51 +08:00
tangxifan 3c6a4d34d8 [core] code format 2023-04-24 13:36:59 +08:00
tangxifan 715765d81b [core] code complete for top testbench generator on ccffv2 upgrades 2023-04-24 13:34:44 +08:00
tangxifan 667d9df028 [core] developing testbench generator for ccff v2 2023-04-24 11:36:21 +08:00
tangxifan 1ba3c56cf3 [core] code format 2023-04-23 16:49:19 +08:00
tangxifan ba90f5020b [core] fixed some bugs which cause netlist generation failed 2023-04-23 16:48:14 +08:00
tangxifan 28b7a12f68 [core] code format 2023-04-23 14:31:35 +08:00
tangxifan bd511ba515 [core] fixed syntax errors 2023-04-23 14:26:08 +08:00
tangxifan 592765af48 [core] code complete for upgrading netlist generator w.r.t. ccff v2 2023-04-23 13:57:37 +08:00
tangxifan 5500b9a289 [core] upgrading netlist generator 2023-04-22 16:27:27 +08:00
tangxifan ea8ae29b53 [core] code format 2023-04-22 15:12:38 +08:00
tangxifan 297a23dee7 [core] fixed syntax errors 2023-04-22 15:09:39 +08:00
tangxifan 5e8e982334 [core] finished developing checkers 2023-04-22 12:44:34 +08:00
tangxifan f70cc32824 [core] developing checkers for configuration protocol w.r.t. the programming clocks 2023-04-22 08:46:36 +08:00
tangxifan aeeee6d8bd [core] code format 2023-04-20 15:07:54 +08:00
tangxifan 40598d25a3 [core] fixed a bug which causes multi-clock programmable network failed in routing 2023-04-20 15:05:45 +08:00
tangxifan 928c7d5736 Merge branch 'master' into xt_clk_arch 2023-04-19 22:17:33 +08:00
tangxifan 9690cea115 [core] fix clang syntax 2023-04-19 15:46:42 +08:00
tangxifan cb4512b925 [core] code format 2023-04-19 11:10:42 +08:00
tangxifan a84cc52d7c [core] fixed a few bugs due to the changes in vtr regarding flat router 2023-04-19 11:08:18 +08:00
tangxifan 11f09db556 [core] fixed a bug where clock tracks do not pass through at higher level 2023-03-07 15:05:56 -08:00
tangxifan 50e201feeb [core] now clock routing for programmable clock network works for 1 clock design 2023-03-07 13:13:25 -08:00
tangxifan 550e68c68b [core] fixed a bug: node_fan_in seems buggy 2023-03-06 22:26:27 -08:00
tangxifan 2ff3ad61ce [core] format 2023-03-06 21:57:44 -08:00
tangxifan 45107bf14f [core] debugging 2023-03-06 21:48:19 -08:00
tangxifan c23b8e579d [core] fixed a bug 2023-03-06 17:10:14 -08:00
tangxifan 9823983b30 [core] debuggign 2023-03-06 15:57:37 -08:00
tangxifan 1633279c65 [core] fixed a bug in building edges for nodes 2023-03-06 14:50:28 -08:00
tangxifan 953625b1ca [core] format 2023-03-05 22:32:05 -08:00
tangxifan de1e300ec7 [core] now resize rr_node for clock graph is working 2023-03-05 22:21:55 -08:00
tangxifan 81e9187aac [core] debugging 2023-03-03 22:55:14 -08:00
tangxifan 4423d917fa [core] debugging 2023-03-03 18:00:43 -08:00
tangxifan 29ee6e7136 [core] debugging 2023-03-03 17:33:53 -08:00
tangxifan 5a43b451c1 [core] debugging 2023-03-03 16:56:20 -08:00
tangxifan c4ad21451c [core] debugging 2023-03-02 21:54:48 -08:00
tangxifan 46510388be [core] now fabric generator can wire clock ports to routing blocks 2023-03-02 12:33:26 -08:00
tangxifan 974263f0fa [core] dev 2023-03-01 23:27:29 -08:00
tangxifan 099d9f32f4 [core] dev 2023-03-01 16:08:15 -08:00
tangxifan 9baaf9ea06 [core] fix compiler warnings 2023-02-28 20:40:14 -08:00
tangxifan 7732907623 [core] format 2023-02-28 17:01:11 -08:00
tangxifan 2ff8fb8737 [core] wrapping up clock routing command 2023-02-28 16:52:54 -08:00
tangxifan bd2608d3e0 [core] dev 2023-02-28 15:41:37 -08:00
tangxifan 6f2572324e [core] developing route clock rr_graph command 2023-02-28 11:52:38 -08:00
tangxifan 8d5c21b14d [core] code format 2023-02-27 23:00:15 -08:00
tangxifan 2735b708d3 [core] reworked the tapping XML syntax 2023-02-27 22:59:44 -08:00
tangxifan ff69664c14 [core] syntax 2023-02-27 22:39:12 -08:00
tangxifan d4e19edc71 [core] finishing up clock rr_graph appending 2023-02-27 22:31:16 -08:00
tangxifan 2df1609616 [core] add a new API to get pin index from a tile 2023-02-27 21:44:00 -08:00
tangxifan 0dfe96bcf1 [core] dev 2023-02-27 19:37:49 -08:00
tangxifan b3dec93eb9 [core] code format 2023-02-27 15:12:59 -08:00
tangxifan 9ec4d690db [core] clock edges interconnecting clock tracks across levels 2023-02-27 15:10:36 -08:00
tangxifan b6eace8fac [core] now switch id is linked in clock network 2023-02-27 13:10:54 -08:00
tangxifan cae05a14e1 [core] dev 2023-02-26 23:10:50 -08:00
tangxifan 009d711ba5 [core] code format 2023-02-26 22:23:41 -08:00
tangxifan 87a9146082 [core] adding rr spatial lookup for clock nodes only 2023-02-26 22:23:17 -08:00
tangxifan db36f87dfa [core] enhance clock tree arch validation 2023-02-26 18:39:53 -08:00
tangxifan b9e5ae7ae9 [core] developing 2023-02-26 18:31:08 -08:00
tangxifan 780fc0f26d [core] developing validators and annotate rr_segment for clock arch 2023-02-26 18:03:55 -08:00
tangxifan 4bd952027f [core] dev 2023-02-26 15:31:07 -08:00
tangxifan 75773ddd4e [code] format 2023-02-26 12:46:29 -08:00
tangxifan 3db5acfb37 [core] dev 2023-02-26 12:40:13 -08:00
tangxifan 06f77d0435 [core] dev 2023-02-25 22:59:07 -08:00