tangxifan
|
0bec4b3f32
|
[Test] Update task configuration to use proper openfpgashell script
|
2021-04-27 23:34:42 -06:00 |
|
tangxifan
|
7d059f7407
|
[Benchmark] Bug fix in dual port ram 16k benchmark
|
2021-04-27 23:33:20 -06:00 |
|
tangxifan
|
3c1c33bf1e
|
[Benchmark] Add a microbenchmark just fit 16k dual port ram
|
2021-04-27 22:51:43 -06:00 |
|
tangxifan
|
7e2368158e
|
[Benchmark] move benchmarks to microbenchmark category
|
2021-04-27 22:12:30 -06:00 |
|
tangxifan
|
5a85ec9fa0
|
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
|
2021-04-27 22:09:10 -06:00 |
|
tangxifan
|
dd46780865
|
[Script] Update yosys script using BRAMs
|
2021-04-27 21:44:27 -06:00 |
|
tangxifan
|
fdfbdc4613
|
[Test] Update task configuration files to use dedicated yosys script
|
2021-04-27 20:05:04 -06:00 |
|
tangxifan
|
2802b0895c
|
[HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM
|
2021-04-27 19:55:46 -06:00 |
|
tangxifan
|
e67095edd2
|
[HDL] Add 16k-bit dual port ram verilog
|
2021-04-27 19:55:16 -06:00 |
|
tangxifan
|
0f8aaae2bc
|
[Arch] Patch architecture using 16kbit dual port RAM
|
2021-04-27 19:54:34 -06:00 |
ganeshgore
|
3c9c089e64
|
Merge pull request #307 from lnis-uofu/io_map_file
Output I/O mapping information to XML file
|
2021-04-27 17:19:07 -06:00 |
|
tangxifan
|
1d498bb296
|
[Benchmark] Add a scalable micro benchmark fifo
|
2021-04-27 15:26:52 -06:00 |
|
tangxifan
|
8728fd9561
|
[Tool] Typo fix to resolve clang errors
|
2021-04-27 15:06:07 -06:00 |
|
tangxifan
|
1bae59dc6a
|
[Doc] Update documentation for the write_io_mapping command
|
2021-04-27 14:54:57 -06:00 |
|
tangxifan
|
6cb4d7d720
|
[Test] Add the new test to regressiont test
|
2021-04-27 14:41:38 -06:00 |
|
tangxifan
|
b8ced5377f
|
[Test] Add a test case for i/o mapping writer
|
2021-04-27 14:41:15 -06:00 |
|
tangxifan
|
f9fd444b86
|
[Script] Add an write I/O mapping example script for openfpga shell
|
2021-04-27 14:40:26 -06:00 |
|
tangxifan
|
c5d36757c6
|
[Tool] Fix typo in io mapping writing
|
2021-04-27 14:39:57 -06:00 |
|
tangxifan
|
43c1e052ef
|
[Tool] Add a writer to output I/O mapping information to XML files
|
2021-04-27 14:30:16 -06:00 |
|
tangxifan
|
33c12c8f0e
|
Update CMakeLists.txt
|
2021-04-26 20:51:54 -06:00 |
|
tangxifan
|
5296e376f1
|
Merge pull request #305 from lnis-uofu/micro_benchmarks
Test addition for FPGA architecture with multi-width DSP blocks
|
2021-04-26 17:43:56 -06:00 |
|
tangxifan
|
1d5e926d9e
|
[Test] Deploy new test to CI
|
2021-04-26 16:29:54 -06:00 |
|
tangxifan
|
6291871faf
|
[Test] Added a test for the example architecture with 2x2 DSP blocks
|
2021-04-26 16:28:43 -06:00 |
|
tangxifan
|
8c007c7c49
|
[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
|
2021-04-26 16:28:10 -06:00 |
|
tangxifan
|
64704f52eb
|
Merge pull request #304 from lnis-uofu/tileable_rr_graph
Tileable rr graph
|
2021-04-26 14:11:16 -06:00 |
|
tangxifan
|
3b50d00b30
|
Merge branch 'master' into tileable_rr_graph
|
2021-04-26 12:12:57 -06:00 |
|
tangxifan
|
9a8d109d85
|
Merge pull request #303 from lnis-uofu/tangxifan-patch-1
Update PULL_REQUEST_TEMPLATE.md
|
2021-04-26 12:06:23 -06:00 |
|
tangxifan
|
05f08c2f25
|
Update PULL_REQUEST_TEMPLATE.md
|
2021-04-26 12:05:37 -06:00 |
|
tangxifan
|
7d4c5e3cd1
|
[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
|
2021-04-26 12:00:57 -06:00 |
|
tangxifan
|
6e87b8875b
|
[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
|
2021-04-26 11:59:25 -06:00 |
|
tangxifan
|
cbd7105083
|
[Tool] Add illustrative comments to tileable rr_graph generator
|
2021-04-26 11:57:17 -06:00 |
|
tangxifan
|
880624e699
|
[Tool] Update comments in tileable rr_graph generator to be easier to be understood
|
2021-04-26 11:48:02 -06:00 |
|
ganeshgore
|
d7426808ba
|
Merge pull request #299 from hitblunders/master
Updated compile.rst
|
2021-04-26 00:26:07 -06:00 |
|
ganeshgore
|
ab34ebecef
|
Merge pull request #301 from lnis-uofu/tangxifan-patch-1
Update bug_report.md
|
2021-04-26 00:25:26 -06:00 |
|
ganeshgore
|
cb38455a52
|
Merge pull request #302 from lnis-uofu/tangxifan-patch-2
Update pull_request_template.md
|
2021-04-26 00:25:14 -06:00 |
|
tangxifan
|
deb9f4a9f7
|
Update pull_request_template.md
|
2021-04-25 22:11:34 -06:00 |
|
tangxifan
|
a8b2966709
|
Update bug_report.md
|
2021-04-25 22:08:17 -06:00 |
|
tangxifan
|
83167b6b61
|
Update bug_report.md
|
2021-04-25 22:06:13 -06:00 |
|
tangxifan
|
4b8dab0913
|
Update bug_report.md
|
2021-04-25 20:51:29 -06:00 |
|
tangxifan
|
386dbf8c1a
|
Update pull_request_template.md
|
2021-04-25 18:30:48 -06:00 |
|
tangxifan
|
94c575fa74
|
Update bug_report.md
|
2021-04-25 18:12:12 -06:00 |
|
tangxifan
|
1baee10e61
|
Merge pull request #298 from lnis-uofu/micro_benchmarks
Micro benchmarks addition and testing for FPGAs with DSP blocks
|
2021-04-24 17:55:38 -06:00 |
|
tangxifan
|
62dc5a3856
|
[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
|
2021-04-24 16:02:24 -06:00 |
|
tangxifan
|
b7da22501c
|
[Test] Deply new test to regression test
|
2021-04-24 15:55:05 -06:00 |
|
tangxifan
|
5adffad602
|
[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
|
2021-04-24 15:49:53 -06:00 |
|
tangxifan
|
80f98328df
|
[Test] Update test settings for architecture with fracturable DSP blocks
|
2021-04-24 15:16:50 -06:00 |
|
tangxifan
|
8b8096f3a8
|
[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
|
2021-04-24 14:57:09 -06:00 |
|
tangxifan
|
a3a98fa21d
|
[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
|
2021-04-24 14:56:10 -06:00 |
|
tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
|
tangxifan
|
4f454abfde
|
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
|
2021-04-24 14:01:42 -06:00 |