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111 Commits

Author SHA1 Message Date
LNIS-Projects c506e16d33
Update command_line_usage.rst 
Small fix
 2018-12-22 14:46:15 +01:00
LNIS-Projects ba303450e2
Update file_organization.rst 2018-12-22 14:45:00 +01:00
LNIS-Projects 5fa6c84087
New fpga_verilog commands documented 2018-12-22 14:39:51 +01:00
LNIS-Projects 55459f7906
Update index.rst 
Reorganization
 2018-12-10 13:46:38 -07:00
LNIS-Projects 56555fc8a0
Update index.rst 
Removed abc from the project because included in Yosys
 2018-12-10 13:46:02 -07:00
BaudouinChauviere 88af64c606
Update eda_flow.rst 
Distributions compilable added
 2018-12-05 16:29:07 -07:00
BaudouinChauviere 576feb600f
Update eda_flow.rst 
Completed with FPGA-Verilog/Bitstream and corrected few errors
 2018-12-05 16:24:03 -07:00
BaudouinChauviere 0f87fb9c3f
Update file_organization.rst 
Correction on the routing
 2018-12-03 14:21:40 -07:00
BaudouinChauviere e541834bd0
Update file_organization.rst 
Made similar to the SPICE one
 2018-12-03 14:20:34 -07:00
BaudouinChauviere cd301a5bb8
Update file_organization.rst 
Correction of the hierarchy
 2018-12-03 14:09:11 -07:00
BaudouinChauviere 9c97125b0d
Update spice_simulation.rst 
typo
 2018-12-03 13:42:45 -07:00
BaudouinChauviere b8f702e16d
Update file_organization.rst 
Creation of the table for better understanding
 2018-12-03 13:40:42 -07:00
BaudouinChauviere 10cbd2efef
Update index.rst 
Commenting the multi mode out until more mature
 2018-12-03 11:50:13 -07:00
BaudouinChauviere 8e7def7f88
Update link_circuit_modules.rst 
Correction of typos
 2018-12-03 11:39:44 -07:00
BaudouinChauviere f8e801b9d1
Merge pull request #1 from LNIS-Projects/Documentation-Update 
Update index.rst
 2018-12-03 11:27:05 -07:00
BaudouinChauviere a4d29aeb1b
Update circuit_model_examples.rst 
Typo correction
 2018-12-03 11:26:04 -07:00
BaudouinChauviere e39e0219e9
Update circuit_modules.rst 
Move the examples from this part to their own
 2018-12-03 10:59:20 -07:00
BaudouinChauviere 7a49ca8ce2
Update index.rst 
New section in the doc
 2018-12-03 10:58:50 -07:00
BaudouinChauviere 99769c1510
Create circuit_model_examples.rst 
Better architecture of the doc
 2018-12-03 10:58:11 -07:00
BaudouinChauviere 47a214520f
Update index.rst 
Skip lines
 2018-12-03 10:32:15 -07:00
BaudouinChauviere 6827549be2
Update index.rst 
Include the links for the external documentation
 2018-12-03 10:31:02 -07:00
Aurelien Alacchi 4a950c6857 Flatten_hierarchy_doc 2018-10-18 16:28:12 -06:00
Aurelien Alacchi aa5449c37d Verif_modif_doc_title_2 2018-10-17 16:49:55 -06:00
Aurelien Alacchi 6327a4486b Revert "Verif_modif_doc_title" 
This reverts commit 8f7f88ebea.
 2018-10-17 16:47:32 -06:00
Aurelien Alacchi 8f7f88ebea Verif_modif_doc_title 2018-10-17 16:45:42 -06:00
Aurelien Alacchi 2cfbe2b997 FPGA-Verilog_doc_update 2018-10-17 16:38:03 -06:00
Aurelien Alacchi e96c6e2f02 Revert "Bug_correction_fpga-spice_commandLine" 
This reverts commit 33e76d0255.
 2018-10-12 16:09:14 -06:00
Aurelien Alacchi 33e76d0255 Bug_correction_fpga-spice_commandLine 2018-10-12 16:05:53 -06:00
Aurelien Alacchi 26538cb2bc Correction_file_commandline_fpga-spice 2018-10-12 16:03:23 -06:00
Aurelien Alacchi e0c2fc2c8a Documentation_code&example_update 2018-10-12 15:50:09 -06:00
Aurelien Alacchi 07380ed1fa Minor_bug_fig_name_correction 2018-10-09 15:33:30 -06:00
Aurelien Alacchi a43574e593 Update_doc_circuit_level_fig_fixed 2018-10-09 15:29:15 -06:00
Aurelien Alacchi d1c01cd68b Update_bug_fig_doc_CL 2018-10-08 17:54:44 -06:00
Aurelien Alacchi 7c51129a33 test42docFig 2018-10-08 16:20:34 -06:00
Aurelien Alacchi 8723722e99 test_correction_bug_fig_doc_CL 2018-10-08 16:18:56 -06:00
Aurelien Alacchi ebd4b282f5 test_correction_figure 2018-10-08 16:00:21 -06:00
Aurelien Alacchi a318f8e20e Update_doc_circuit_level_bug_image 2018-10-08 15:48:54 -06:00
Aurelien Alacchi f79913f379 Update_doc_circuit_level_bug_image 2018-10-08 15:42:19 -06:00
Aurelien Alacchi 44bdca0429 Revert "figure_correction_doc_circuit_level" 
This reverts commit 046829bd13.
 2018-10-08 15:30:47 -06:00
Aurelien Alacchi 054a2bb186 Revert "bug_correction_fig_circuit_level" 
This reverts commit c6cd63462c.
 2018-10-08 15:30:36 -06:00
Aurelien Alacchi c6cd63462c bug_correction_fig_circuit_level 2018-10-08 15:30:03 -06:00
Aurelien Alacchi 046829bd13 figure_correction_doc_circuit_level 2018-10-08 15:27:30 -06:00
Aurelien Alacchi cf1dddff5f Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-10-08 15:19:48 -06:00
Aurelien Alacchi cf804b8fb2 Define Circuit Level update 2018-10-08 15:15:44 -06:00
LNIS-Projects 05f70548f3
Add files via upload 2018-10-08 15:02:16 -06:00
Baudouin Chauviere 16c0c4656e Adds titles and WiP tags for new parts. Tutorials included 
Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
 2018-09-25 14:53:04 -06:00
Baudouin Chauviere 70d303dfb5 Define Circuit doc improvement 
Added some content, better spacing for understanding and made some changes in the options we show
 2018-09-25 11:53:53 -06:00
tangxifan f47246e8b7 Fixed doc ref problem 2018-09-14 14:02:47 -06:00
tangxifan 087ba475bb debugging bibtex 2018-09-14 13:58:20 -06:00
tangxifan 965835debe debugging doc ref 2018-09-14 13:48:57 -06:00
tangxifan 4afbce10a3 fixing bugs for doc references 2018-09-14 13:44:40 -06:00
tangxifan 5d697da4e7 refine doc hierarchy 2018-09-14 13:27:05 -06:00
唐希凡 0bfbc9b0aa update docs 2018-09-14 13:11:51 -06:00
Xifan Tang 44e63ec98b Test new template 2018-09-13 23:00:56 -06:00
Xifan Tang fec0daa2a8 Update a draft 2018-09-13 22:58:54 -06:00
唐希凡 0f31d51c1a update doc html template 2018-09-13 17:59:53 -06:00
唐希凡 655baa3cd9 Debugged Doc 2018-09-13 17:39:57 -06:00
Xifan Tang cea41801da updating documentation 2018-09-13 16:25:24 -06:00
Xifan Tang c94cc01c83 debugging documentation 2018-09-13 15:52:08 -06:00
Xifan Tang 7261a53f3c update docs theme 2018-09-13 15:48:10 -06:00
Xifan Tang d6d6951496 Adding documentation 2018-09-13 15:38:41 -06:00