tangxifan
|
ed5d83178f
|
add fundamental check codes for LbRRGraph
|
2020-02-19 21:07:31 -07:00 |
|
tangxifan
|
bc27f9dd0c
|
add check codes for nets inside LbRouter
|
2020-02-19 20:34:30 -07:00 |
|
tangxifan
|
43f15e4d6f
|
add methods to LbRouter for nets to be routed and access to routing traceback
|
2020-02-19 16:40:53 -07:00 |
|
tangxifan
|
444b994285
|
flatten the t_net inside LbRouter into internal data
|
2020-02-19 15:37:22 -07:00 |
|
tangxifan
|
2b37fcb296
|
use strong id for nets to be routed in LbRouter
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2020-02-19 15:09:25 -07:00 |
|
tangxifan
|
2f1bcdd27d
|
use local data to store illegal modes for pb_graph_node inside LbRouter
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2020-02-19 14:53:35 -07:00 |
|
tangxifan
|
5ccb4adb08
|
refactored LB router main function
|
2020-02-19 11:09:24 -07:00 |
|
tangxifan
|
3d5a15d41e
|
refactored most functions except echo and try_route() in LbRouter
|
2020-02-19 00:07:36 -07:00 |
|
tangxifan
|
80fa6f8a0a
|
refactored skip nets in LbRouter
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2020-02-18 22:08:51 -07:00 |
|
tangxifan
|
289c869caf
|
refactored expand rt_node in LbRouter
|
2020-02-18 22:01:22 -07:00 |
|
tangxifan
|
c7ef14fc23
|
refactoring node expansion in LbRouter
|
2020-02-18 21:51:03 -07:00 |
|
tangxifan
|
11879d43b4
|
add methods one by one to LbRouter from cluster_router.cpp
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2020-02-18 19:22:36 -07:00 |
|
tangxifan
|
0310dafe42
|
add accessors to LBRouter
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2020-02-18 18:35:00 -07:00 |
|
tangxifan
|
1799db810d
|
compilation error fix
|
2020-02-18 17:04:36 -07:00 |
|
tangxifan
|
d58d14df8e
|
start encapsulate the whole lb router in an object
|
2020-02-18 16:50:56 -07:00 |
|
tangxifan
|
ed25ccc70f
|
start refactoring lb router in openfpga namespace
|
2020-02-18 12:00:27 -07:00 |
|
tangxifan
|
ef11482a95
|
fix dependency error in pack_types header file
|
2020-02-18 11:36:16 -07:00 |
|
tangxifan
|
098f7dddf3
|
Merge branch 'refactoring' into dev
|
2020-02-18 11:04:22 -07:00 |
|
tangxifan
|
6060440b97
|
fine tuning for the verbose output
|
2020-02-17 21:14:15 -07:00 |
|
tangxifan
|
409b3f6896
|
add lb_rr_graph builder for the refactored version
|
2020-02-17 21:11:56 -07:00 |
|
tangxifan
|
8e97443410
|
start working on repack
|
2020-02-17 17:57:43 -07:00 |
|
tangxifan
|
62e4f14e30
|
add lb_rr_graph to device annotation
|
2020-02-17 17:26:27 -07:00 |
|
tangxifan
|
6c69b52ded
|
Add missing file
|
2020-02-17 17:11:29 -07:00 |
|
tangxifan
|
92076c1460
|
refactored lb_rr_graph in the same principle of RRGraph object
|
2020-02-17 16:59:24 -07:00 |
|
tangxifan
|
95accb662b
|
Merge branch 'refactoring' into dev
|
2020-02-16 16:36:20 -07:00 |
|
tangxifan
|
60f40a9657
|
use constant module manager as much as possible in Verilog writer
|
2020-02-16 16:35:26 -07:00 |
|
tangxifan
|
11775c370b
|
bring FPGA top module verilog writer online. Fabric Verilog generator done
|
2020-02-16 16:18:14 -07:00 |
|
tangxifan
|
e37ac8a098
|
add grid module Verilog writer
|
2020-02-16 16:04:41 -07:00 |
|
tangxifan
|
c20caa1fa3
|
routing module Verilog writer is online
|
2020-02-16 14:47:54 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
99c3712b6f
|
adapt Verilog wire module writer
|
2020-02-16 12:59:37 -07:00 |
|
tangxifan
|
5cc68b0730
|
adapt LUT Verilog writer
|
2020-02-16 12:45:58 -07:00 |
|
tangxifan
|
105ccabecc
|
adapt memroy writer for verilog
|
2020-02-16 12:41:43 -07:00 |
|
tangxifan
|
c9d8120ae0
|
adapt Verilog mux writer
|
2020-02-16 12:35:41 -07:00 |
|
tangxifan
|
a88c4bc954
|
add decode utils to libopenfpga and adapt local decoder writer in Verilog
|
2020-02-16 12:21:59 -07:00 |
|
tangxifan
|
3efd1a2a6d
|
print verilog module writer online
|
2020-02-16 12:04:03 -07:00 |
|
tangxifan
|
cf34339e96
|
adapt essential gates for submodule generation
|
2020-02-16 11:57:19 -07:00 |
|
tangxifan
|
2eba882332
|
put verilog submodules online. ready to bring the how submodule writer online
|
2020-02-16 11:41:20 -07:00 |
|
tangxifan
|
2035afc34b
|
Merge branch 'refactoring' into dev
|
2020-02-16 00:04:29 -07:00 |
|
tangxifan
|
4cb61e2138
|
bring preprocessing flag Verilog netlists online
|
2020-02-16 00:03:24 -07:00 |
|
tangxifan
|
0d5292ad0d
|
adapt verilog writer utils
|
2020-02-15 23:26:59 -07:00 |
|
tangxifan
|
bf54be3d00
|
add option data structure for FPGA Verilog
|
2020-02-15 21:39:47 -07:00 |
|
tangxifan
|
da79ef687c
|
add missing files
|
2020-02-15 20:54:37 -07:00 |
|
tangxifan
|
8b0df8632c
|
bring fpga verilog create directory online
|
2020-02-15 20:38:45 -07:00 |
|
tangxifan
|
622c7826d1
|
start transplanting fpga_verilog
|
2020-02-15 15:03:00 -07:00 |
|
tangxifan
|
45914e8afa
|
Merge branch 'refactoring' into dev
|
2020-02-15 14:14:54 -07:00 |
|
tangxifan
|
85627dc128
|
put build top module online
|
2020-02-15 14:13:32 -07:00 |
|
tangxifan
|
539f13720a
|
tile direct supports inter-column/inter-row direct connections
|
2020-02-15 13:42:53 -07:00 |
|
tangxifan
|
ee8f5542e9
|
Merge branch 'refactoring' into dev
|
2020-02-14 22:22:04 -07:00 |
|
tangxifan
|
213c611c0b
|
add tile direct builder
|
2020-02-14 22:21:32 -07:00 |