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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan 73386dd1a9 refactored the Verilog header generation 2019-12-04 17:55:05 -07:00
tangxifan 696d4a9522 remove useless channel wire module generation 2019-11-05 16:10:00 -07:00
tangxifan 2b829238b5 refactored wire Verilog generation 2019-09-12 20:49:02 -06:00