tangxifan
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42b528be57
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doc updates
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2019-08-21 15:11:25 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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b207050b03
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minor fix in documentation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
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fc93a4941a
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update documentation
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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7603850d72
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complete documentation for new features
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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8a046394f8
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add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
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Xifan Tang
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afd78604c9
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Merge branch 'dev' into documentation: resolved conflicts and add logo files
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2019-07-17 17:50:11 -04:00 |
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Xifan Tang
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e7b40f06b0
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Add documentation for fracturable LUTs
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2019-07-17 15:21:07 -04:00 |
AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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AurelienUoU
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df53f6da2c
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Updates FPGA-Verilog command lines
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2019-07-05 13:41:34 -06:00 |
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AurelienUoU
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9e99048815
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Update documentation
Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
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2019-07-05 11:56:02 -06:00 |
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AurelienUoU
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27dbc527a0
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Update Readme
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2019-07-05 11:06:55 -06:00 |
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AurelienUoU
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f56adc6815
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Update documentation
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2019-07-05 10:20:16 -06:00 |
BaudouinChauviere
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cb34ac0243
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Update sc_flow.rst
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2019-04-01 16:30:31 -06:00 |
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BaudouinChauviere
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361bbc13e3
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Update func_verify.rst
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2019-04-01 16:29:42 -06:00 |
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BaudouinChauviere
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a176bf3a19
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Update file_organization.rst
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2019-04-01 16:28:48 -06:00 |
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BaudouinChauviere
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01371ce54d
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Update customize_subckt.rst
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2019-04-01 16:27:06 -06:00 |
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BaudouinChauviere
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1ea7ec3265
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Update spice_simulation.rst
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2019-04-01 16:26:02 -06:00 |
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BaudouinChauviere
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cfdc072164
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Update file_organization.rst
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2019-04-01 16:25:09 -06:00 |
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BaudouinChauviere
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fcc3bf0967
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Update command_line_usage.rst
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2019-04-01 16:23:24 -06:00 |
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BaudouinChauviere
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f4b72bd4e1
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Update link_circuit_modules.rst
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2019-04-01 16:21:59 -06:00 |
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BaudouinChauviere
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ce300c196c
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Update circuit_modules.rst
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2019-04-01 16:13:23 -06:00 |
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BaudouinChauviere
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6e065ef3b3
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Update tech_lib.rst
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2019-04-01 16:09:31 -06:00 |
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BaudouinChauviere
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aed779ca3d
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Update spice_sim_setting.rst
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2019-04-01 16:08:00 -06:00 |
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BaudouinChauviere
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4900caaed9
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Update generality.rst
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2019-04-01 16:04:17 -06:00 |
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BaudouinChauviere
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33df25366c
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Update eda_flow.rst
Correction fix
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2019-04-01 16:02:47 -06:00 |
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BaudouinChauviere
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d6261f1f59
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Update motivation.rst
Typo and better explanations correction
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2019-04-01 15:57:04 -06:00 |
Baudouin Chauviere
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39f7b0b9a2
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Update of the doc for better fit with the current version
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2019-04-01 11:55:28 -06:00 |
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BaudouinChauviere
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5dbcfa6d70
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Repair broken link
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2019-01-03 18:26:30 +01:00 |
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BaudouinChauviere
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28010f6c91
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Testing another link method
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2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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30f2ada557
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Repaired broken links
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2019-01-03 18:18:03 +01:00 |
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LNIS-Projects
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77dd7f3e04
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correction of the name of the figure
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2018-12-29 01:45:45 +01:00 |
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LNIS-Projects
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0f6ac32f43
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Further resizing
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2018-12-29 01:44:24 +01:00 |
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LNIS-Projects
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38a3b01520
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Resize the images
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2018-12-29 01:42:43 +01:00 |
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Baudouin Chauviere
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9ee50de26a
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Adding information on the layout
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2018-12-29 01:14:26 +01:00 |
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Baudouin Chauviere
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0a5391c14f
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Addition of some illustrations
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2018-12-26 18:16:16 +01:00 |
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LNIS-Projects
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de7d646fa0
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Update func_verify.rst
Functional Verification documentation
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2018-12-26 18:05:24 +01:00 |
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LNIS-Projects
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c0626e9a1c
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Adding the Verification Step from ModelSim
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2018-12-26 18:00:03 +01:00 |
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LNIS-Projects
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c506e16d33
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Update command_line_usage.rst
Small fix
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2018-12-22 14:46:15 +01:00 |
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LNIS-Projects
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ba303450e2
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Update file_organization.rst
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2018-12-22 14:45:00 +01:00 |
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LNIS-Projects
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5fa6c84087
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New fpga_verilog commands documented
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2018-12-22 14:39:51 +01:00 |
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LNIS-Projects
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55459f7906
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Update index.rst
Reorganization
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2018-12-10 13:46:38 -07:00 |
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LNIS-Projects
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56555fc8a0
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Update index.rst
Removed abc from the project because included in Yosys
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2018-12-10 13:46:02 -07:00 |
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BaudouinChauviere
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88af64c606
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Update eda_flow.rst
Distributions compilable added
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2018-12-05 16:29:07 -07:00 |
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BaudouinChauviere
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576feb600f
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Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
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2018-12-05 16:24:03 -07:00 |
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BaudouinChauviere
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0f87fb9c3f
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Update file_organization.rst
Correction on the routing
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2018-12-03 14:21:40 -07:00 |
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BaudouinChauviere
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e541834bd0
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Update file_organization.rst
Made similar to the SPICE one
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2018-12-03 14:20:34 -07:00 |
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BaudouinChauviere
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cd301a5bb8
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Update file_organization.rst
Correction of the hierarchy
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2018-12-03 14:09:11 -07:00 |
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BaudouinChauviere
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9c97125b0d
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Update spice_simulation.rst
typo
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2018-12-03 13:42:45 -07:00 |
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BaudouinChauviere
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b8f702e16d
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Update file_organization.rst
Creation of the table for better understanding
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2018-12-03 13:40:42 -07:00 |