5 Commits

Author	SHA1	Message	Date
tangxifan	4d2a3680be	support bus explicit port mapping to standard cells (for BRAMs)	2019-06-14 11:09:15 -06:00
tangxifan	0902d1e75a	c++ string is not working, use char which is stable	2019-06-13 18:38:46 -06:00
tangxifan	af1628abfe	use bus port for primitives in Verilog generator	2019-06-13 16:26:58 -06:00
Baudouin Chauviere	2019840d7c	cleaned unused variables	2019-05-13 14:45:02 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00