tangxifan
|
f002f7e30f
|
add const 0 and 1 module Verilog generation
|
2019-10-21 14:17:09 -06:00 |
|
tangxifan
|
b2f57ecf81
|
plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
|
2019-10-21 00:00:30 -06:00 |
|
tangxifan
|
520e145af2
|
move mux_lib to fpga_x2p_setup
|
2019-10-19 19:13:52 -06:00 |
|
tangxifan
|
04f0fbebf7
|
plug in module graph to feed verilog writers
|
2019-10-18 21:59:22 -06:00 |
|
tangxifan
|
7c1bce4b59
|
add module builders for essential gates
|
2019-10-18 20:41:05 -06:00 |
|
tangxifan
|
3b82d62d03
|
start developing module graph builders
|
2019-10-18 20:02:02 -06:00 |
|
tangxifan
|
db38f21412
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
tangxifan
|
8c1158fc5c
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
tangxifan
|
4171a674b1
|
refactored clb2clb direct connects for cross-column/row
|
2019-10-17 23:06:59 -06:00 |
|
tangxifan
|
190449c06f
|
refactoring top-level module with clb2clb direct connection
|
2019-10-17 17:29:04 -06:00 |
|
tangxifan
|
c9d8311a93
|
bug fixing for grid-gsb connections in top module when using compact routing
|
2019-10-15 18:00:55 -06:00 |
|
tangxifan
|
6a13120208
|
rename grid modules to be clear
|
2019-10-15 16:28:46 -06:00 |
|
tangxifan
|
071757dc52
|
add module nets to connect grids and sbs
|
2019-10-15 16:08:51 -06:00 |
|
tangxifan
|
f779ad7ecf
|
bug fixing for global and gpio port wiring; start refactoring top-level module
|
2019-10-14 15:53:04 -06:00 |
|
tangxifan
|
6793c67c8d
|
refactored pb_type and grid Verilog generation
|
2019-10-13 21:07:30 -06:00 |
|
tangxifan
|
b581399761
|
add memory ports and nets to intermediate pb_types
|
2019-10-13 17:45:32 -06:00 |
|
tangxifan
|
cab4bd6807
|
add gpio ports to pb_type modules
|
2019-10-13 16:23:22 -06:00 |
|
tangxifan
|
d1948c82eb
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
tangxifan
|
b3ca0d32a4
|
remove configuration bus naming dependency on SRAM circuit models
|
2019-10-11 19:47:36 -06:00 |
|
tangxifan
|
73a5977e0d
|
Debugged Verilog generation for primitive pb_types
|
2019-10-11 18:00:37 -06:00 |
|
tangxifan
|
50f7d1eae3
|
bug fixing in Verilog port merging and instanciation
|
2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
|
refactorint net addition for configuration signals in module graph
|
2019-10-11 13:07:14 -06:00 |
|
tangxifan
|
c9950162d1
|
start plug in new Verilog writer. Start debugging
|
2019-10-10 22:02:46 -06:00 |
|
tangxifan
|
1f650aac73
|
add local direct connection Verilog code generation
|
2019-10-10 20:54:31 -06:00 |
|
tangxifan
|
f2b3341d87
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
|
developing verilog writer for modules
|
2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
edad988ebb
|
add net accessor and mutators to module manager
|
2019-10-09 21:14:30 -06:00 |
|
tangxifan
|
557d8b60f3
|
start implementing module graph-based connection
|
2019-10-09 20:30:16 -06:00 |
|
tangxifan
|
9cb6e64ab3
|
refactoring instanciation inside primitive pb_type Verilog module
|
2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
|
2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
ea2942640e
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
|
2019-10-08 12:10:26 -06:00 |
|
tangxifan
|
173b886314
|
add module name generation for pb_types
|
2019-10-07 21:09:54 -06:00 |
|
tangxifan
|
3ca6f08aa4
|
start refactoring physical block Verilog generation
|
2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
|
refactored shared config bits calculation
|
2019-10-06 16:57:53 -06:00 |
|
tangxifan
|
393f0b0ac3
|
align formal verification port inside refactored routing blocks
|
2019-10-05 21:16:48 -06:00 |
|
tangxifan
|
c920047ee8
|
refactored Verilog generation for connection blocks
|
2019-10-05 18:14:23 -06:00 |
|
tangxifan
|
2d7e8d9811
|
add check codes for memory buses
|
2019-10-05 11:07:26 -06:00 |
|
tangxifan
|
6b301d9f44
|
Merge branch 'dev' into refactoring
|
2019-10-04 22:47:29 -06:00 |
|
tangxifan
|
b905c0c68c
|
refactored memory module Verilog generation for scan-chains
|
2019-10-04 22:45:45 -06:00 |
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
633a12ee08
|
Buggy version but need help on debugging
|
2019-10-01 14:49:42 -06:00 |
|
tangxifan
|
b082e60c10
|
start refactoring instanciation of memory modules
|
2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
|
simplify the local wire generation for ccffs
|
2019-09-28 21:36:56 -06:00 |
|
tangxifan
|
1983e56557
|
make local configuration bus generation more general
|
2019-09-28 21:02:14 -06:00 |
|
tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
|
2019-09-27 23:10:43 -06:00 |
|
tangxifan
|
4da5035627
|
Connect CCFFs in a chain in a Verilog module
|
2019-09-27 20:50:12 -06:00 |
|
tangxifan
|
1e187f3d15
|
start adding memory circuit to Switch blocks
|
2019-09-27 18:08:37 -06:00 |
|
tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
|
2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
8ccf681749
|
Merge branch 'dev' into refactoring
|
2019-09-26 21:00:19 -06:00 |