tangxifan
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5fe039dd7c
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[Regression Tests] Deploy the fully connected crossbar test to CI
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2020-09-16 17:35:49 -06:00 |
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tangxifan
|
35d47ee0e7
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[Regression tests] bug fix in the test case for fully connected output crossbar
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2020-09-16 17:33:54 -06:00 |
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tangxifan
|
030d7f02f8
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[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
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2020-09-16 17:30:08 -06:00 |
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tangxifan
|
30fb99095f
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[Regression Tests] Add new test case for fully connected output crossbar
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2020-09-16 17:29:15 -06:00 |
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tangxifan
|
3c0faf0021
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[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
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2020-09-16 17:27:24 -06:00 |
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tangxifan
|
8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
|
b43cd2741d
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[Regression Tests] Add gcc-5 compatibility test to Travis CI
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2020-09-14 20:14:16 -06:00 |
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tangxifan
|
c23742c751
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 20:13:27 -06:00 |
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tangxifan
|
fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
|
d4bac95cd4
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[Regression Tests] Enable matrix eval parameter in setting up compilers
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2020-09-14 17:07:14 -06:00 |
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tangxifan
|
c08d4f5cd9
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[Regression Test] Patch travis script
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2020-09-14 16:59:08 -06:00 |
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tangxifan
|
e3559f0df9
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[Regression Test] Add compiler coverage test to CI
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2020-09-14 16:53:16 -06:00 |
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tangxifan
|
c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
|
2020-09-14 16:16:03 -06:00 |
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tangxifan
|
f149c88548
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[Regression Test] Deploy input buffer only multiplexer testcase to CI
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2020-09-14 16:11:48 -06:00 |
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tangxifan
|
f42411c29e
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[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
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2020-09-14 16:03:43 -06:00 |
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tangxifan
|
aaf63050bb
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
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2020-09-14 15:58:34 -06:00 |
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tangxifan
|
aa9521b23b
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
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2020-09-14 15:57:44 -06:00 |
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tangxifan
|
a03f2fe974
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[Regression Test] Deploy the debuf mux test case to CI
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2020-09-14 15:48:08 -06:00 |
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tangxifan
|
eecfd186f0
|
[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
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2020-09-14 15:46:10 -06:00 |
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tangxifan
|
9bf0e772a3
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[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
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2020-09-14 15:45:35 -06:00 |
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tangxifan
|
7a2502ddf9
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[documentation] add more guidelines about the vpr-openfpga architecture annotation
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2020-09-02 22:47:14 -06:00 |
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tangxifan
|
04070fd4ca
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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tangxifan
|
b5251ce5af
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[documentation] update motivation figure and layout licenses
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2020-09-01 11:07:50 -06:00 |
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tangxifan
|
4b3142c4ee
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[Architecture File] Patch openfpga architecture with default circuit model definition
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2020-08-23 15:13:28 -06:00 |
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tangxifan
|
9101ba1021
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[Architecture Language] Update openfpga architecture files for default models
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2020-08-23 14:55:44 -06:00 |
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tangxifan
|
ac8e937a50
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[Documentation] Update for default circuit model rules
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2020-08-23 14:08:38 -06:00 |
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tangxifan
|
9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
|
2020-08-23 14:06:03 -06:00 |
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tangxifan
|
b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
|
fb5a5a2448
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[documentation] remove the limitation on through channels
|
2020-08-19 20:12:49 -06:00 |
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tangxifan
|
6c925dcded
|
[regression test] Add more tests for thru channels and deploy to CI
|
2020-08-19 20:11:37 -06:00 |
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tangxifan
|
1a3e020174
|
deploy through channel test case to CI
|
2020-08-19 20:04:01 -06:00 |
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tangxifan
|
8041c90f12
|
bug fix in through channel support in tileable routing
|
2020-08-19 20:01:50 -06:00 |
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tangxifan
|
881672d46a
|
update thru channel arch for avoid buggy pin locations
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2020-08-19 19:52:35 -06:00 |
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tangxifan
|
47f15729ad
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update doc about the limitation on using tileable routing
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2020-08-19 18:37:28 -06:00 |
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tangxifan
|
d6d17675e2
|
update docoumentation about the constraints when using tileable rr_graph generator
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2020-08-19 18:01:32 -06:00 |
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tangxifan
|
bf08e1841c
|
add new test case using thru channels
|
2020-08-19 17:58:34 -06:00 |
|
tangxifan
|
f3ca1c0973
|
fix rr_graph on thru routing channel support
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2020-08-19 17:28:25 -06:00 |
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tangxifan
|
f0bc6f83f1
|
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
|
2020-08-19 15:34:59 -06:00 |
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tangxifan
|
18735894f9
|
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
|
2020-08-19 15:27:30 -06:00 |
|
tangxifan
|
3273f441fe
|
bug fix in the flagship vpr arch
|
2020-08-19 15:23:20 -06:00 |
|
tangxifan
|
aa4a9b28cc
|
start testing the initial offset in the flagship architecture
|
2020-08-19 15:03:46 -06:00 |
|
tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
|
tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
|
2020-08-19 14:43:44 -06:00 |
|
tangxifan
|
f631245b2b
|
bug fix and enriched debugging info print out
|
2020-08-19 13:41:04 -06:00 |
|
tangxifan
|
79b6ff3cb0
|
relax checking for device annotation as we support multi-port during physical mode pin mapping
|
2020-08-19 12:44:51 -06:00 |
|
tangxifan
|
f64079641d
|
bug fix in flagship vpr arch with frac mem and dsp
|
2020-08-19 12:43:58 -06:00 |
|
tangxifan
|
af1c7c6f29
|
start fixing the bug in thru channels
|
2020-08-19 12:18:35 -06:00 |
|
tangxifan
|
d7efdf35b6
|
add custom pin location to the flagship vpr arch with frac mem and dsp
|
2020-08-19 11:15:25 -06:00 |
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tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
tangxifan
|
743167521a
|
add Verilog design for fracturable 32k memory
|
2020-08-18 21:13:46 -06:00 |