5 Commits

Author	SHA1	Message	Date
tangxifan	56ab63d939	[Documentation] Fix format in table	2020-10-06 12:02:15 -06:00
tangxifan	113708c68f	[Documentation] Reorganization the overview part by adding technical highlights	2020-10-06 11:56:10 -06:00
tangxifan	67300af987	[Documentation] Update motivation with new set of figures	2020-09-29 16:52:16 -06:00
tangxifan	aa77ee9af6	add tutorial for full testbench run	2020-06-11 19:31:09 -06:00
tangxifan	dcce782a46	update documentation about Verilog testbenches	2020-06-11 19:31:08 -06:00