4 Commits

Author	SHA1	Message	Date
tangxifan	b6bb433edc	bug fixing for datapath mux size in Verilog generation	2019-09-03 18:09:21 -06:00
tangxifan	8fc258cc93	develop and plug mux_lib_builder, refactoring the mux submodule generation	2019-08-25 15:33:37 -06:00
tangxifan	69039aa742	developed subgraph extraction and start refactoring mux generation	2019-08-20 15:24:53 -06:00
tangxifan	893683fa95	start developing mux library	2019-08-20 15:24:53 -06:00