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OpenFPGA
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3,630 Commits 70 Branches 8 Tags 105 MiB
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892 Commits

Author SHA1 Message Date
tangxifan 3a5c26c6a1 [Test] Update IWLS test by using new architecture and customize DFF techmap 2021-04-21 19:51:25 -06:00
tangxifan 8cbea6a268 [HDL] Add technology library for customizable DFF synthesis 2021-04-21 19:50:51 -06:00
tangxifan 3d615e1516 [Script] Add yosys script supporting customize DFF/BRAM/DSP mapping 2021-04-21 19:50:07 -06:00
tangxifan 9d9840d9b7 [Arch] Add architecture using multi-mode DFFs 2021-04-21 19:49:48 -06:00
tangxifan 8046b16c15 [Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing 2021-04-21 14:04:34 -06:00
tangxifan b203ef7bc2 [Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs 2021-04-21 14:03:51 -06:00
tangxifan 2fa370d7d5 [Test] Patch regression tests for fpga bitstream 2021-04-19 17:15:14 -06:00
tangxifan 64163edbe6 [Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting 2021-04-19 16:15:25 -06:00
tangxifan 578d81b67a [Test] Patch task configuration file 2021-04-19 16:15:00 -06:00
tangxifan 18eb5c9de9 [Test] Deploy new test to CI 2021-04-19 15:56:41 -06:00
tangxifan 5976cc0a1c [Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection 2021-04-19 15:54:18 -06:00
tangxifan 7018073e28 [Script] Update openfpga shell script w/o ace usage to adapt pin constraint files 2021-04-17 15:04:51 -06:00
tangxifan da95da933b [Test] Add pin constraint file to map reset to correct FPGA pins 2021-04-17 15:04:26 -06:00
tangxifan e3dafe99da [Arch] Revert to old version arch due to editing by mistake 2021-04-16 20:58:32 -06:00
tangxifan c020333512
Merge branch 'master' into dff_techmap 2021-04-16 20:54:28 -06:00
tangxifan 7172fc9ea1 [Test] Patch test for architecture using asynchronous DFFs 2021-04-16 20:48:37 -06:00
tangxifan 0a15f366cb [HDL] Patch dff models used in yosys tech map 2021-04-16 20:48:15 -06:00
tangxifan 16e02ef485 [Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script 2021-04-16 20:47:39 -06:00
tangxifan 1c2f91b7e6 [Script] Patch yosys script with dff tech map 2021-04-16 20:47:18 -06:00
tangxifan 2666726f36 [Script] Remove clock routing from example openfpga shell script without ace 2021-04-16 20:46:49 -06:00
tangxifan 23d08757cf [Script] Add example script without using ACE2 2021-04-16 20:20:10 -06:00
tangxifan bbdc0e53af [Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures 2021-04-16 20:14:48 -06:00
tangxifan b11d03f9c5 [Test] Deploy new test to CI 2021-04-16 20:01:40 -06:00
tangxifan 93be81abe1 [Test] Add test case for architecture using DFF with reset 2021-04-16 20:00:48 -06:00
tangxifan 5414a6a3da [Script] Add yosys script with custom DFF tech mapping 2021-04-16 20:00:30 -06:00
tangxifan 4239bb4e68 [Arch] Patch architecture files using multi-mode DFFs 2021-04-16 19:59:55 -06:00
tangxifan f2f7f010ea [Arch] Add new architectures using DFF with reset in VPR 2021-04-16 19:26:18 -06:00
tangxifan 64294ae4eb [Doc] Update README for architecture files due to new architecture features 2021-04-16 19:25:54 -06:00
tangxifan ff4460695b [HDL] Add dff tech map files for yosys 2021-04-16 17:00:55 -06:00
tangxifan e46c6e75a3 [Benchmark] Add missing RTL for IWLS2005 benchmarks 2021-04-16 16:50:41 -06:00
tangxifan 87587bbb74 [Test] Add iwls2005 benchmarks to regression tests 2021-04-16 16:12:05 -06:00
tangxifan 1566a5558a [Test] Add task configuration file for iwls2005 2021-04-16 16:10:31 -06:00
tangxifan 43bf016576 [Script] Add example openfpga shell script for iwls benchmark 2021-04-16 16:09:47 -06:00
tangxifan 26d3b5a954 [Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches 2021-04-16 16:08:58 -06:00
tangxifan 86ad572530 [Benchmark] Add opencore RTLs from IWLS 2005 benchmarks 2021-04-16 14:27:54 -06:00
tangxifan b469705819
Merge branch 'master' into fpga_sdc_test 2021-04-11 21:14:46 -06:00
tangxifan 1db8bd7eec [Test] Update regression test with new SDC tests 2021-04-11 20:24:32 -06:00
tangxifan 07f6066c11 [Script] Update timing unit in SDC example script 2021-04-11 20:24:18 -06:00
tangxifan 94c4c817eb [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
tangxifan a4893e27cf [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification 2021-04-11 17:26:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan b00b4f0f5f [HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian 2021-03-23 15:44:53 -06:00
tangxifan d82ffe0cbf [Test] Deploy MAC_8 benchmark to regression test 2021-03-23 15:36:28 -06:00
tangxifan 108c84a022 [HDL] Add HDL for 8-bit single-mode multiplier 2021-03-23 15:36:09 -06:00
tangxifan 145a80de43 [Script] Add an openfpga shell script for heterogeneous fpga verification 2021-03-23 15:35:34 -06:00
tangxifan fdec72b5bc [Arch] Add an example architecture with 8-bit single-mode multiplier 2021-03-23 15:35:06 -06:00
tangxifan be03eafd66 [Benchmark] Add a micro benchmark: 8-bit multiply and accumulate 2021-03-23 15:33:37 -06:00
tangxifan 8c970a792a [Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier 2021-03-23 15:33:00 -06:00
tangxifan 6b0409da60 [Script] Add a template yosys script support only DSP mapping 2021-03-23 15:32:10 -06:00
tangxifan a4bbffd1aa [HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA 2021-03-23 15:30:41 -06:00