Commit Graph

852 Commits

Author SHA1 Message Date
tangxifan 5a40c6713d managed to plug in refactored essential gates, dead codes to be removed 2019-08-21 21:50:26 -06:00
tangxifan d8eb9866a0 refactored gate verilog generation 2019-08-21 18:49:48 -06:00
tangxifan b08ff465c9 refactored pass-gate verilog generation 2019-08-21 17:33:16 -06:00
tangxifan 1a15b9efd4 update travis settings 2019-08-21 15:27:07 -06:00
tangxifan 5e156dc725 minor fix for OSX and update travis using ccache to speed up compilation 2019-08-21 15:25:36 -06:00
tangxifan 42b528be57 doc updates 2019-08-21 15:11:25 -06:00
tangxifan 9c43b1b753 complete refacotriing the inv and buf part in submodules 2019-08-21 14:54:05 -06:00
Ganesh Gore 764d7039b5 Import utils bug fixing for travis test 2019-08-21 12:42:58 -06:00
Ganesh Gore 2f0acfad23 Updated travis to run regression task 2019-08-21 11:09:53 -06:00
Ganesh Gore e51ff44710 Added execution time information in logs 2019-08-21 11:08:47 -06:00
Ganesh Gore a335a57c6c Added debug option to commnad line arguments 2019-08-21 11:08:13 -06:00
tangxifan a40e5c91ca refactored power-gate inverter 2019-08-20 21:56:55 -06:00
tangxifan 19472ace4e renaming files 2019-08-20 21:01:38 -06:00
tangxifan 59f1ac7310 add missing files and try to refactor submodule essential 2019-08-20 20:49:26 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 60e8d2b29f add missing files and try to refactor submodule essential 2019-08-20 16:13:08 -06:00
Ganesh Gore 66a3d97698 Merge branch 'ganesh_dev' into dev 2019-08-20 16:00:41 -06:00
Ganesh Gore b7484ef178 Removed traces of old template file 2019-08-20 15:58:19 -06:00
tangxifan 29104b6fa5 rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
tangxifan a7ac1e4980 remame methods in circuit_library 2019-08-20 15:24:53 -06:00
tangxifan 69039aa742 developed subgraph extraction and start refactoring mux generation 2019-08-20 15:24:53 -06:00
tangxifan bee070d7cc start plug in MUX library 2019-08-20 15:24:53 -06:00
tangxifan 893683fa95 start developing mux library 2019-08-20 15:24:53 -06:00
tangxifan 153d506abb add graph-based mux decoding function 2019-08-20 15:24:52 -06:00
tangxifan dcca9f4f0f finish mux graph builders 2019-08-20 15:24:52 -06:00
tangxifan 638969c3c9 adding mux graph data structures 2019-08-20 15:24:52 -06:00
tangxifan 0b8473e960 start developing graphs for muxes, with aims to simplify netlist and bitstream generation 2019-08-20 15:24:52 -06:00
Ganesh Gore 69ffc38645 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-19 21:59:06 -06:00
Ganesh Gore afee2229af Removed unused templates and file from openfpga_flow directory 2019-08-19 21:32:52 -06:00
Ganesh Gore 08b0ef3550 Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
Ganesh Gore 53941eaf5c Changed yosys output file name 2019-08-19 19:06:46 -06:00
Ganesh Gore 8d0153d34e Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
Ganesh Gore 616d7706c9 Added list of intermidiate files filename 2019-08-19 19:05:08 -06:00
Ganesh Gore 8f8707ff98 Added option to filter results after parsing 2019-08-19 19:04:14 -06:00
Ganesh Gore 5116aa2ae1 Added architecture and replaced variables 2019-08-19 19:02:50 -06:00
Ganesh Gore cb5b16c949 Moved required files to openfpga folder 2019-08-19 18:57:42 -06:00
Ganesh Gore 6dc05b769b Added Power Model Files 2019-08-19 18:55:23 -06:00
Ganesh Gore 7f6c1b3e00 Code re-arrangement
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
Ganesh Gore fb29fcfc06 Added build files in .gitignore 2019-08-17 22:59:54 -06:00
Ganesh Gore 12c998c12a Added dockerignore + minor changes in openfpga_flow script 2019-08-17 16:22:52 -06:00
Ganesh Gore 66bb8a5e4b Updated RRAM architecture file 2019-08-17 02:20:04 -06:00
Ganesh Gore 7bfc48b8e4 Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
Ganesh Gore 125d7888df Merge remote-tracking branch 'origin/spice_model_refactoring' into ganesh_dev 2019-08-16 22:00:41 -06:00
tangxifan aa7f3bef7f fixed bugs in configure pb_rr_graph and dependence on testbenches 2019-08-16 18:20:30 -06:00
tangxifan e456b6f905 replace spice_models with circuit model in bitstream generator 2019-08-16 16:36:49 -06:00
tangxifan 5ece7ab6d0 start refactoring the bitstream part using spice_models 2019-08-16 15:58:14 -06:00
tangxifan b66e120366 patch on local encoders for unused configuration, avoid chip-burn issues 2019-08-16 15:32:23 -06:00
Ganesh Gore 4865335627 Merge remote-tracking branch 'origin/dev' into ganesh_dev 2019-08-16 14:14:16 -06:00
Ganesh Gore c43c3cdf25 Added VPR output parse option 2019-08-16 13:36:39 -06:00
Ganesh Gore effbd332aa Added task report generation 2019-08-16 10:59:44 -06:00