tangxifan
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167778cf57
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refactoring MUX Verilog instanciation in Switch block
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2019-09-27 16:05:47 -06:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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ab6f1a5461
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add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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69039aa742
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developed subgraph extraction and start refactoring mux generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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893683fa95
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start developing mux library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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153d506abb
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add graph-based mux decoding function
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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dcca9f4f0f
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finish mux graph builders
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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638969c3c9
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adding mux graph data structures
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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0b8473e960
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start developing graphs for muxes, with aims to simplify netlist and bitstream generation
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2019-08-20 15:24:52 -06:00 |