ganeshgore
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890ead91b9
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Fixed modelsim include references
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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ea4122a8a4
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Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
AurelienUoU
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09fd2afa9c
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
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Ganesh Gore
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f05aede868
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Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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Ganesh Gore
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27005d6640
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Added Modelsim Python Script
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2019-11-01 18:20:40 -06:00 |
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Ganesh Gore
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d269472daf
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Updated formality python script
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2019-09-27 14:00:57 -06:00 |
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Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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Ganesh Gore
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f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
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Ganesh Gore
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30cbe38d3d
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Added Test Modes - Added blif VPR Option
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2019-08-22 17:00:59 -06:00 |
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Ganesh Gore
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afee2229af
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Removed unused templates and file from openfpga_flow directory
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2019-08-19 21:32:52 -06:00 |
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Ganesh Gore
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08b0ef3550
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Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
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2019-08-19 21:28:23 -06:00 |
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Ganesh Gore
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616d7706c9
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Added list of intermidiate files filename
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2019-08-19 19:05:08 -06:00 |
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Ganesh Gore
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8f8707ff98
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Added option to filter results after parsing
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2019-08-19 19:04:14 -06:00 |
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Ganesh Gore
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cb5b16c949
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Moved required files to openfpga folder
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2019-08-19 18:57:42 -06:00 |
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Ganesh Gore
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5d3708651e
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Added fpga_flow and fpga_task script
+ Missed local intermediate commits
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2019-08-15 14:39:58 -06:00 |
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Ganesh Gore
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9ab57d1b2e
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |