4 Commits

Author	SHA1	Message	Date
tangxifan	744d87cb4e	[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues	2021-02-26 09:34:52 -07:00
tangxifan	8853370c60	[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file	2021-02-04 20:20:10 -07:00
tangxifan	d3397f6936	[Script] Remove activity from bitstream setting example script	2021-02-02 09:25:36 -07:00
tangxifan	7f14dfbe87	[Script] Add example script to use bitstream setting	2021-02-02 09:18:08 -07:00