tangxifan
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35d6c9661b
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Finish the first version of XML parser for design technology of circuit models
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2020-01-14 16:24:27 -07:00 |
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tangxifan
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5937ffc809
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add XML parsing for buffer/pass-gate-logic -related properties
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2020-01-14 15:44:24 -07:00 |
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tangxifan
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56113e1aab
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adding XML parsing for design tech of circuit model
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2020-01-14 14:10:00 -07:00 |
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tangxifan
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2692d0fc35
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adding XML parsing for SPICE and Verilog netlist for each circuit model
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2020-01-14 08:45:27 -07:00 |
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tangxifan
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82d83ddceb
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reorganized the read XML openfpga arch
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2020-01-14 08:33:48 -07:00 |