tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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4367dba9b7
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move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
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2020-02-11 21:02:58 -07:00 |