tangxifan
|
0d62661c71
|
bug fixing and spot critical bugs in directlist parser
|
2019-06-23 20:52:38 -06:00 |
tangxifan
|
cdd4af9c58
|
vpr likes the tileable rr_graph while fpga_x2p does not
|
2019-06-23 18:11:13 -06:00 |
tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
tangxifan
|
2837f44df2
|
bug fixing for tileable rr_graph generator.
|
2019-06-22 20:41:06 -06:00 |
tangxifan
|
7c38b32eb1
|
keep bug fixing for tileable rr_graph generator
|
2019-06-21 22:51:11 -06:00 |
tangxifan
|
1b91c32121
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-21 17:59:55 -06:00 |
tangxifan
|
41954056ce
|
many bug fixing for tileable rr_graph generator. Still debugging
|
2019-06-21 17:58:46 -06:00 |
AurelienUoU
|
0a42f6a796
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-21 15:47:14 -06:00 |
AurelienUoU
|
c0d7099cd6
|
Allow CB on top of blocks with height > 1
|
2019-06-21 15:46:05 -06:00 |
tangxifan
|
d48fd959a9
|
keep bug fixing for tileable rr_graph generator
|
2019-06-20 22:30:26 -06:00 |
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
tangxifan
|
cf82d87e11
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-20 18:18:20 -06:00 |
tangxifan
|
baab9c4a21
|
basically finished the coding of tileable rr_graph generator. testing to go
|
2019-06-20 18:17:07 -06:00 |
Baudouin Chauviere
|
be25b6dd66
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-20 14:11:03 -06:00 |
Baudouin Chauviere
|
3bd6c40a10
|
Report timing modified to have only one liners
|
2019-06-20 14:10:39 -06:00 |
AurelienUoU
|
a7502bb43b
|
Avoid configuration bits for module wihch don't require them
|
2019-06-20 09:40:41 -06:00 |
tangxifan
|
e7f2bd3b7c
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-19 21:31:54 -06:00 |
tangxifan
|
2f15d2d13c
|
keep developing tileable rr_graph, track2ipin and opin2track to go
|
2019-06-19 21:30:16 -06:00 |
AurelienUoU
|
ff00e4c79c
|
Free only if it's possible to free
|
2019-06-19 16:15:30 -06:00 |
tangxifan
|
ba15358564
|
developing ipin2track mapping for tiles
|
2019-06-18 18:06:21 -06:00 |
tangxifan
|
9ca1b42f4c
|
developing switch block pattern for tileable routing architecture
|
2019-06-18 16:52:42 -06:00 |
tangxifan
|
352c97302b
|
start building object GSB graph
|
2019-06-17 22:10:30 -06:00 |
tangxifan
|
f4191315da
|
use rr_gsb to build edges of rr_graph
|
2019-06-17 18:01:45 -06:00 |
tangxifan
|
51ff150a77
|
bug fixing in tileable rr_graph generator
|
2019-06-17 10:16:08 -06:00 |
tangxifan
|
0d14fef53e
|
bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
|
2019-06-16 23:02:18 -06:00 |
tangxifan
|
04ffb99ca6
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-16 16:01:30 -06:00 |
Baudouin Chauviere
|
57a4ad1f99
|
Break memories even in the clb sdc
|
2019-06-16 14:27:29 -06:00 |
tangxifan
|
1af3b5ef55
|
set chan_rr_nodes in tileable rr_graph builder
|
2019-06-16 14:23:19 -06:00 |
tangxifan
|
8c9cc003ea
|
developing routing track rr_node set up in tileable routing architecture
|
2019-06-15 18:11:08 -06:00 |
Xifan Tang
|
155c8d4924
|
fix CMakeList bug in disabling VPR graphics
|
2019-06-15 13:21:25 -06:00 |
tangxifan
|
d19b470b33
|
Merge branch 'tileable_routing' into multimode_clb
Conflicts:
vpr7_x2p/vpr/regression_verilog.sh
|
2019-06-15 12:25:30 -06:00 |
tangxifan
|
c8bf456097
|
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
|
2019-06-15 12:23:36 -06:00 |
tangxifan
|
d3296d0975
|
developing tileable rr_graph builder
|
2019-06-14 22:35:42 -06:00 |
tangxifan
|
a33627606e
|
developing tileable routing track arrangement
|
2019-06-14 17:35:40 -06:00 |
AurelienUoU
|
29dadc51b4
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-14 11:46:02 -06:00 |
AurelienUoU
|
c76dbaac33
|
Update regression test avoiding overwritting files
|
2019-06-14 11:44:44 -06:00 |
tangxifan
|
4d2a3680be
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
tangxifan
|
0902d1e75a
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
tangxifan
|
5f61cd8876
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
Conflicts:
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
|
2019-06-13 16:32:39 -06:00 |
tangxifan
|
af1628abfe
|
use bus port for primitives in Verilog generator
|
2019-06-13 16:26:58 -06:00 |
tangxifan
|
dddbbac85c
|
merge from multimode_clb bug fixing
|
2019-06-13 15:59:34 -06:00 |
AurelienUoU
|
15b4cc9ecb
|
Error correction in memory generation for pb_types without modes
|
2019-06-13 15:34:25 -06:00 |
tangxifan
|
43128ad3f0
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
tangxifan
|
5ae4dec0af
|
fix bugs in CMakeList on enable/disable VPR Graphics
|
2019-06-12 22:48:00 -06:00 |
tangxifan
|
1d00e3665b
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:50:40 -06:00 |
tangxifan
|
65b5454f3a
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:49:10 -06:00 |
AurelienUoU
|
bf13c1f731
|
Add a script to create a new file with correct path rather than overwrite the existing
|
2019-06-11 14:28:58 -06:00 |
Ganesh Gore
|
1da363f7f1
|
Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev
|
2019-06-11 11:59:54 -06:00 |
tangxifan
|
7245917b9c
|
fix a bug for iopad SPICE generation
|
2019-06-11 11:43:56 -06:00 |
Ganesh Gore
|
1093e341a8
|
Added additional architecure files
|
2019-06-11 11:26:44 -06:00 |
tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
tangxifan
|
8e3ad675e0
|
use sstream for rr_block verilog writer
|
2019-06-10 16:23:35 -06:00 |
tangxifan
|
009e5244d3
|
minor fix on the port direction of configuration peripherals for memory decoders
|
2019-06-10 15:39:35 -06:00 |
tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
|
2019-06-10 15:29:44 -06:00 |
tangxifan
|
e4f70771a2
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
tangxifan
|
8a8f4153ce
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
tangxifan
|
e31407f693
|
start cleaning up SDC generator with new RRGSB data structure
|
2019-06-10 10:57:26 -06:00 |
tangxifan
|
17bc7fc296
|
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
|
2019-06-08 20:11:22 -06:00 |
Xifan Tang
|
61e359efc5
|
Enable an option to disable/enable graphics in VPR compilation
|
2019-06-08 15:08:17 -06:00 |
tangxifan
|
90696def6d
|
remove vpr Makefile
|
2019-06-07 23:44:39 -06:00 |
tangxifan
|
d737c4ff46
|
fix path in regression test! TODO: must keep a duplicated copy for template.xml
|
2019-06-07 23:31:42 -06:00 |
tangxifan
|
f5b6ee6adf
|
update travis configuration and clean up repository
|
2019-06-07 22:19:11 -06:00 |
tangxifan
|
8c5ec4572d
|
revert string to sprintf
|
2019-06-07 20:20:41 -06:00 |
tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
tangxifan
|
44ce0e8834
|
update gsb unique module detection and fix formal verification port direction
|
2019-06-07 17:18:38 -06:00 |
tangxifan
|
24d53390d8
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
tangxifan
|
c9f810ceb6
|
update rr_gsb to build connection blocks
|
2019-06-07 11:01:55 -06:00 |
tangxifan
|
472aff5acb
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
tangxifan
|
ce9fc5696c
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
tangxifan
|
8c1e7b799f
|
fixed critical bugs in Connection Block Unique Module detection
|
2019-06-06 16:31:50 -06:00 |
tangxifan
|
4f543c510c
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-06 12:50:03 -06:00 |
tangxifan
|
873e4d989f
|
fine-tuning Verilog format and node addition to rr_blocks
|
2019-06-06 12:48:41 -06:00 |
AurelienUoU
|
182d49da45
|
Update regression test scripts
|
2019-06-06 11:47:51 -06:00 |
tangxifan
|
c2de0eefb1
|
fix redundant comma in SB Verilog module
|
2019-06-06 09:15:05 -06:00 |
tangxifan
|
b9e1b1afc4
|
fix a critical bug in num_reserved_sram_ports
|
2019-06-05 17:31:01 -06:00 |
tangxifan
|
aaf8d23971
|
fix critical bugs in routing submodules
|
2019-06-05 16:43:18 -06:00 |
tangxifan
|
01e075377d
|
fix typo in Verilog generation
|
2019-06-05 15:30:34 -06:00 |
tangxifan
|
21d0cb52bc
|
Merge remote-tracking branch 'origin' into tileable_sb
|
2019-06-05 13:31:49 -06:00 |
tangxifan
|
24ca3104b0
|
fix minor bugs in Switch Block submodules
|
2019-06-05 13:30:55 -06:00 |
tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
|
2019-06-05 12:56:05 -06:00 |
AurelienUoU
|
84fabbd43b
|
Fix sdc analysis bug related to virtual nodes + add the option in regression test
|
2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
|
d24488092d
|
Fix bug
|
2019-06-05 11:40:04 -06:00 |
tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
|
2019-06-04 17:47:40 -06:00 |
AurelienUoU
|
a2f6ded2a2
|
Add path modification in file changing a keyword into OpenFPGA full path
|
2019-06-04 15:21:15 -06:00 |
tangxifan
|
98b82c17be
|
bug fixing for clear RRSwitchBlock
|
2019-06-04 14:02:49 -06:00 |
tangxifan
|
2c6780ab92
|
add side mirror detection for RRSwitchBlock
|
2019-06-04 13:01:22 -06:00 |
AurelienUoU
|
813470d459
|
Test Cmake fix
|
2019-06-03 10:31:44 -06:00 |
AurelienUoU
|
7368e6d7e4
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-31 11:01:07 -06:00 |
AurelienUoU
|
737300eb54
|
Fix regression test
|
2019-05-31 11:00:30 -06:00 |
Baudouin Chauviere
|
1932d00309
|
Correction of the SDC to remove global clocks
|
2019-05-30 15:04:21 -06:00 |
AurelienUoU
|
ba05a08ef0
|
Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
|
2019-05-30 09:52:19 -06:00 |
AurelienUoU
|
46fa1197b0
|
Test reading tech file
|
2019-05-29 16:43:56 -06:00 |
AurelienUoU
|
74ee6bad7f
|
Update spice path in architecture
|
2019-05-29 10:08:58 -06:00 |
tangxifan
|
5b15a746d3
|
add num_driver_nodes to Switch Block XML writter
|
2019-05-28 20:52:33 -06:00 |
tangxifan
|
5ed076dfb4
|
fixed a critical bug in rotating
|
2019-05-28 17:55:09 -06:00 |
tangxifan
|
9cc5518d5a
|
keep adding segment information for SB XML outputter
|
2019-05-28 15:59:55 -06:00 |
tangxifan
|
e7e18eb4c1
|
Add more information in SB XML outputter
|
2019-05-28 15:56:41 -06:00 |
tangxifan
|
ca363da30c
|
add options to specify output directory of SB XML
|
2019-05-28 15:19:10 -06:00 |
tangxifan
|
6b51b42ee7
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-28 14:53:44 -06:00 |
tangxifan
|
af91fca1e0
|
add rr_blocks XML writer to help debugging Switch Block Rotation
|
2019-05-28 14:52:44 -06:00 |
Baudouin Chauviere
|
3da216f297
|
correction Null issue for the flat model
|
2019-05-28 14:15:24 -06:00 |
AurelienUoU
|
ffdcd4bb9c
|
Path correction 2
|
2019-05-28 11:59:09 -06:00 |
tangxifan
|
c75ffa858b
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-28 11:26:16 -06:00 |
tangxifan
|
6f30d3ad05
|
support rotation on segment groups inside RRChan and improve rotatable mirror searching
|
2019-05-28 11:25:16 -06:00 |
AurelienUoU
|
20f80a73e7
|
Correct path to tech files
|
2019-05-28 11:24:03 -06:00 |
tangxifan
|
0f5666ea11
|
fixed the bug in mirror node direction
|
2019-05-27 21:58:21 -06:00 |
tangxifan
|
eece161d58
|
keep debugging on Switch Block rotation
|
2019-05-27 21:10:30 -06:00 |
tangxifan
|
5720217cfd
|
Add copy constructor for RRChan, RRSwitchBlock etc.
|
2019-05-27 15:44:34 -06:00 |
tangxifan
|
1bea9870fc
|
developed new rotating methods for RRSwitchBlocks, debugging ongoing
|
2019-05-26 23:35:30 -06:00 |
tangxifan
|
4b852afeac
|
skip rotating mirror detection which is too time-consuming
|
2019-05-25 23:41:46 -06:00 |
tangxifan
|
22e71f5847
|
Add rotate one side of switch block functionality
|
2019-05-25 22:48:07 -06:00 |
tangxifan
|
858a323228
|
Add more support for rotating Switch Blocks
|
2019-05-25 21:26:35 -06:00 |
tangxifan
|
2eab0b1c1c
|
update unique_mirror search algorithm for Switch Blocks
|
2019-05-25 19:54:15 -06:00 |
tangxifan
|
d3eae80e64
|
implemented an native way in finding rotable Switch blocks
|
2019-05-25 19:37:18 -06:00 |
tangxifan
|
ae0248fbc6
|
debugging SwitchBlock rotating
|
2019-05-24 23:10:30 -06:00 |
tangxifan
|
9adc2945c8
|
add rotate functionality for RRSwitchBlock
|
2019-05-24 21:40:16 -06:00 |
tangxifan
|
02b48d036d
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
tangxifan
|
2c46da6888
|
clean-up warnings Verilog routing generator
|
2019-05-24 16:29:17 -06:00 |
tangxifan
|
27b996337a
|
fixed a critical bug in Compact Verilog generation for SB/CBs
|
2019-05-24 16:14:46 -06:00 |
tangxifan
|
1ade1f1d3f
|
update SDC generator disabled_unused_mux by using RRSwitchBlock
|
2019-05-24 15:42:00 -06:00 |
tangxifan
|
f27b88db8d
|
Use RRChan in SDC generator to replace old data structures
|
2019-05-24 15:34:56 -06:00 |
tangxifan
|
27c234711e
|
clean up warnings in SDC pb_type generator
|
2019-05-24 15:23:38 -06:00 |
tangxifan
|
924136e7a2
|
Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
|
2019-05-24 15:10:08 -06:00 |
tangxifan
|
994b90ae53
|
updated report_timing for using RRSwitchBlock
|
2019-05-24 14:25:51 -06:00 |
tangxifan
|
eef1312325
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |
tangxifan
|
8f4f590ff9
|
update Verilog compact_netlist outputter with RRSwitchBlock classes
|
2019-05-23 21:52:12 -06:00 |
tangxifan
|
ea8c36ce6e
|
upgrade Verilog SB generator using the RRSwitchBlock
|
2019-05-23 17:37:39 -06:00 |
tangxifan
|
4aab93b729
|
update class rr_switch_block and be ready for updating the downstream verilog generator
|
2019-05-22 22:04:31 -06:00 |
tangxifan
|
502344b13a
|
add missing files
|
2019-05-22 12:35:12 -06:00 |
tangxifan
|
efbc454cdd
|
Add Class for RRSwtichBlock and plug-in to replace the old t_sb
|
2019-05-22 12:34:06 -06:00 |
tangxifan
|
ec3b4c86c4
|
update file organization and be ready for SB/CB class
|
2019-05-21 12:15:38 -06:00 |
tangxifan
|
8186d6dd11
|
reorganize files and clean some warnings
|
2019-05-21 10:17:54 -06:00 |
tangxifan
|
b185a17359
|
add routing_channel unique module generation
|
2019-05-20 22:33:17 -06:00 |
giacomin
|
ceee28226e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-20 16:47:07 -06:00 |
giacomin
|
8b520349e7
|
fixed a bug for rram based fpga when using explicit verilog port mapping
|
2019-05-20 16:44:47 -06:00 |
AurelienUoU
|
4f921b03da
|
Add travis full path to avoid missing sources
|
2019-05-16 15:51:10 -06:00 |
AurelienUoU
|
f31339bb5c
|
Correctly instantiate script variables
|
2019-05-16 14:30:16 -06:00 |
AurelienUoU
|
57d75520a6
|
Verilog verification with Travis
|
2019-05-15 15:57:05 -06:00 |
AurelienUoU
|
e44e228153
|
Force graphics to false
|
2019-05-15 15:01:54 -06:00 |
AurelienUoU
|
f940c4fd59
|
Third try to fix issues with graphics on mac
|
2019-05-15 13:22:14 -06:00 |
AurelienUoU
|
a55886a4d9
|
Second try to fix travis autotest adding x11 in macos packages
|
2019-05-15 09:28:29 -06:00 |
AurelienUoU
|
1961b18d14
|
Fix CMakeList to avoid MacOS build failure
|
2019-05-14 18:15:13 -06:00 |
AurelienUoU
|
99beeb48cc
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 16:42:27 -06:00 |
AurelienUoU
|
a3656dde45
|
Add missing Verilog source, Archictecture folder and Testbenches correction
|
2019-05-13 16:41:35 -06:00 |
Baudouin Chauviere
|
b48a27acf0
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 14:45:57 -06:00 |
Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
tangxifan
|
3313eac23b
|
add rr_chan obj
|
2019-05-10 22:50:08 -06:00 |
AurelienUoU
|
9c05a4fb0a
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-10 14:09:23 -06:00 |
AurelienUoU
|
ff9b84d800
|
Bug fix in Icarus requirement
|
2019-05-10 14:07:32 -06:00 |
tangxifan
|
be4643b8a6
|
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
|
2019-05-10 10:21:06 -06:00 |
tangxifan
|
5c646f5de7
|
fix bugs in routing identification
|
2019-05-09 21:40:06 -06:00 |
tangxifan
|
a9df922412
|
finish the identification on mirror switch and connection blocks
Verilog generator to be updated
|
2019-05-09 21:31:39 -06:00 |
tangxifan
|
a3c3f2b892
|
developing compact routing hierarchy
|
2019-05-08 20:49:21 -06:00 |
tangxifan
|
4c6639218e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-08 14:30:33 -06:00 |
tangxifan
|
e305e60ee4
|
minor fix on the shell interface of VPR
|
2019-05-08 14:29:58 -06:00 |
Baudouin Chauviere
|
4f386de2ef
|
gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
|
2019-05-06 17:25:29 -06:00 |
Baudouin Chauviere
|
7ddfe60721
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-06 16:12:52 -06:00 |
Baudouin Chauviere
|
3b62f8e024
|
Conversion from s to ns for the loop breaking delays
|
2019-05-06 16:12:30 -06:00 |
BaudouinChauviere
|
cd4dc8b2e8
|
Delete read_xml_arch_file.c
Already present in SRC
|
2019-05-06 12:55:18 -06:00 |
Baudouin Chauviere
|
a5a1a376ab
|
Modified code for cleaner delay naming convention
|
2019-05-06 12:52:49 -06:00 |
Baudouin Chauviere
|
e7b1d89985
|
Change syntax name for loop_breaker_delay_before/after which is more explicit
|
2019-05-06 12:25:26 -06:00 |
Baudouin Chauviere
|
7c257ebda7
|
Fix on the makefile which was not targetting the right folder
|
2019-05-06 12:21:53 -06:00 |
tangxifan
|
6e6ae1cc3d
|
fixed bugs in CMakeLists.txt and Makefile
|
2019-05-03 23:03:04 -06:00 |
tangxifan
|
4e3487b691
|
Add latest abc and update ace dependence
|
2019-05-03 18:56:03 -06:00 |
tangxifan
|
70b66e0799
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 14:22:20 -06:00 |
Baudouin Chauviere
|
7860042276
|
added before after loop breaker constraining
|
2019-05-03 14:00:06 -06:00 |
tangxifan
|
11cf30b239
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-03 11:54:35 -06:00 |
tangxifan
|
5a97e3e602
|
update Makefile t
|
2019-05-03 11:48:41 -06:00 |
Baudouin Chauviere
|
4e330ee463
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-03 10:43:22 -06:00 |
Baudouin Chauviere
|
921b694400
|
Bug fix sdc breaking loop of edges outside current interconnect
|
2019-05-03 10:42:35 -06:00 |
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
|
2019-05-03 10:24:02 -06:00 |
tangxifan
|
974af5a2ae
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-04-30 14:30:38 -06:00 |
tangxifan
|
42daadee2f
|
critical bug fixing
|
2019-04-30 14:30:17 -06:00 |
Baudouin Chauviere
|
1ab4688339
|
Create no segment constraint in loop_breaker if none is given by user
|
2019-04-30 12:30:07 -06:00 |
tangxifan
|
c46c0fc97d
|
bug fixing for SDC generator
|
2019-04-26 14:07:44 -06:00 |
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
tangxifan
|
8eeb144f32
|
Streamline Makefile and Travis for Mac OS
|
2019-04-10 15:22:20 +08:00 |
Baudouin Chauviere
|
c4b42726c4
|
fixes easing thehandling by the user.
|
2019-03-31 07:55:05 -06:00 |
tangxifan
|
b06df18a89
|
Update rr_graph_area.c
|
2019-03-11 21:46:42 +08:00 |
AurelienUoU
|
213f94ddee
|
Correct preconfiguration
|
2019-01-31 16:43:47 -07:00 |
tangxifan
|
5e36aa82c5
|
fixa bug in determining mux structure
|
2019-01-22 13:54:50 -07:00 |
Baudouin Chauviere
|
f3e7ae0823
|
Hot fix
|
2019-01-10 17:37:15 -07:00 |
tangxifan
|
b8187bbca5
|
fix a bug for supporting default circuit_model of LUTs and FFs
|
2019-01-10 15:10:05 -07:00 |
Baudouin Chauviere
|
4ae3aa517c
|
go.sh replaces the paths now
|
2019-01-09 23:16:43 -07:00 |
Baudouin Chauviere
|
510c27f816
|
Removed commercial scripts, replaced by academia ones
|
2019-01-09 11:56:07 -07:00 |
Baudouin Chauviere
|
3b4fc16c60
|
Adding help message on the go.sh
|
2019-01-09 11:54:28 -07:00 |
tangxifan
|
66701838ff
|
update relative path in ARCH XML
|
2019-01-08 11:41:24 -07:00 |
AurelienUoU
|
b80e435548
|
Correct manual testbench generation bug
|
2019-01-07 18:03:56 -07:00 |
AurelienUoU
|
7ff245448b
|
Add new benchmark and modify go.sh to use it
|
2018-12-26 04:24:26 -07:00 |
AurelienUoU
|
21dc8a006f
|
Change simulator script generation (waves)
|
2018-12-14 14:40:04 -07:00 |
tangxifan
|
ee6b1d6cd6
|
adapt arch xml and act for demo
|
2018-12-13 22:46:40 -07:00 |
tangxifan
|
3d9e913e4e
|
add a benchmark fifo
|
2018-12-12 16:45:33 -07:00 |
AurelienUoU
|
cc5a01d476
|
Fix waveform generation + add benchmark and update go.sh
|
2018-12-11 22:21:39 -07:00 |
AurelienUoU
|
a70b0ac9ac
|
Correct go.sh
|
2018-12-11 15:51:21 -07:00 |
AurelienUoU
|
317c3b59c9
|
Update go.sh and upload pip_add.v
|
2018-12-11 15:47:05 -07:00 |
AurelienUoU
|
fb0992bd85
|
Update go.sh and Makefile
|
2018-12-11 15:31:32 -07:00 |
AurelienUoU
|
c2c4e78639
|
Add pip_add benchmark
|
2018-12-11 15:29:48 -07:00 |
AurelienUoU
|
f5ea3ff233
|
Add an autochecked configuration free testbench
|
2018-12-11 14:44:13 -07:00 |
tangxifan
|
72fbd8d6a8
|
update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |