Commit Graph

200 Commits

Author SHA1 Message Date
tangxifan 513f7800aa [test] update golden outputs for no_cout_in_gsb testcase 2022-11-03 17:51:51 -07:00
tangxifan a88bc2d4de [test] update golden outputs for device4x4 2022-11-03 17:51:08 -07:00
tangxifan 5f74367c2e [test] update golden for device1x1 no time stamp netlists 2022-11-03 17:48:40 -07:00
tangxifan 00a485cbeb [test] add missing file 2022-10-17 19:44:25 -07:00
tangxifan 609e096b1a [test] added a new test to validate explicit port direction in pin table support 2022-10-17 15:25:19 -07:00
tangxifan 8b00bfdff9 [test] replace hardcoded paths in task config files with relative paths 2022-10-17 11:55:57 -07:00
tangxifan aa78981e37 [test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory 2022-10-17 11:18:21 -07:00
tangxifan b0be27b384 [test] add repack design constraints files 2022-10-13 11:22:48 -07:00
tangxifan 7f67794787 [arch]add new arch to test 2022-10-13 10:54:40 -07:00
tangxifan 4eaecde0b9 [test] add golden netlists to ensure no cout in gsb 2022-10-01 11:03:13 -07:00
tangxifan 78f30cf072 [test] add a new test to track the golden netlists where cout is not in GSB 2022-09-30 15:38:27 -07:00
tangxifan 3f8e2ade2e [script] update missing scripts required by pb_pin_fixup test cases 2022-09-29 13:39:46 -07:00
tangxifan 49fa783914 [script] now suggest to skip pb_pin_fixup step in example scripts for most test cases 2022-09-29 10:45:27 -07:00
tangxifan b532bca9d2 [script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment 2022-09-21 10:54:16 -07:00
tangxifan 36603f9772
Merge branch 'master' into vtr_upgrade 2022-09-20 21:08:06 -07:00
tangxifan b8f1520367 [test] fixed a bug 2022-09-20 18:12:23 -07:00
tangxifan 4e254a304d [test] now golden netlists have no relationship with OPENFPGA_PATH 2022-09-20 18:10:52 -07:00
tangxifan 5e23be19a5 [test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths 2022-09-20 18:07:31 -07:00
tangxifan 1b0b50b928 [test] update golden netlist 2022-09-20 16:04:05 -07:00
tangxifan 846ca26311 [test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks 2022-09-20 12:08:24 -07:00
tangxifan 10e86d334a [test] add test cases to validate the various layouts where I/Os are in the center of the grid 2022-09-16 10:29:19 -07:00
tangxifan 330785635d [test] now use a bigger fabric for the test case on custom I/O location 2022-09-13 17:53:33 -07:00
tangxifan 0d6e4e3979 [test] add a new example for the repack options 2022-09-12 16:21:49 -07:00
tangxifan 1ab7590603 [test] added a new test case to 2022-09-09 16:59:06 -07:00
tangxifan d4523e819c [test] fixed a bug 2022-09-08 16:55:50 -07:00
tangxifan d76f3e3b6c [test] fixed the bug 2022-09-08 16:34:23 -07:00
tangxifan 218e6d0a47 [arch] fixed syntax errors 2022-09-08 16:31:52 -07:00
tangxifan a840aeea7a [test] add a new test to validate custom I/O location syntax and deploy to basic regression tests 2022-09-08 16:27:11 -07:00
tangxifan 477e2119d7 [test] remove abs paths in golden outputs without time stamps 2022-09-06 15:24:43 -07:00
tangxifan 93ab992187 [test] update golden outputs without time stamps 2022-09-06 14:59:00 -07:00
tangxifan 561d0a6545 [test] add more test case to track golden outputs for representative fpga sizes 2022-09-06 14:04:23 -07:00
tangxifan 51dc082bd4 [test] force a fixed routing chan W for no time stamp test case 2022-09-01 15:02:40 -07:00
tangxifan d86eb04c5d [test] now no timestamp test case covers gsb files 2022-09-01 14:03:51 -07:00
tangxifan 069e2b00b1 [test] add more test cases to validate gsb options 2022-08-29 22:03:06 -07:00
tangxifan 8b17bf1b1c [test] add a new test case to validate that .act file is not required when power analysis flow is off 2022-08-01 18:44:47 -07:00
tangxifan 35fe858035 [test] fixed a few bugs 2022-07-28 12:06:16 -07:00
tangxifan ca9122ddb9 [test] fixed a bug 2022-07-28 11:57:47 -07:00
tangxifan ec31e124b7 [test] reworked test case on pcf2place 2022-07-28 11:51:56 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan 6719a9aa26 [test] update golden netlists/testbenches etc. 2022-05-22 13:03:01 +08:00
tangxifan 22c4d72358 [test] add a test case to validate negative edge-triggered ff 2022-05-09 16:57:42 +08:00
tangxifan efc25aa66e [Script] Fixed a bug in wrong paths 2022-04-13 16:04:33 +08:00
tangxifan 5beefda3bd [Test] Add a new test case to validate the fix_pins option 2022-04-13 15:55:21 +08:00
tangxifan f8845f7d3a [Test] Add a test case to validate separated clock pins in global port 2022-03-20 11:02:07 +08:00
tangxifan fdaf97e60d [Test] Update test case by using GPIO with config_done signals 2022-02-24 09:49:34 -08:00
tangxifan a615c9d4e3 [Test] Rename test cases 2022-02-24 09:43:41 -08:00
tangxifan b27a04eb24 [Test] Now test case has a config done CCFF 2022-02-23 22:07:11 -08:00
tangxifan 245c7b1e45 [Test] Add a new test case to validate config enable signal in preconfigured testbenches 2022-02-23 16:02:00 -08:00
tangxifan e33ba667e4 [Test] Add missing file 2022-02-20 10:59:44 -08:00
tangxifan f30de1085c [Test] Cover all the related testcase about bus group 2022-02-19 23:33:16 -08:00