AurelienUoU
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c51001c853
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Add compilation verification task in openfpga_flow
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2020-01-23 13:13:23 -07:00 |
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AurelienUoU
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85c9f26a9f
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Update documentation about cmake version and graphical interface
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2020-01-22 20:46:49 -07:00 |
tangxifan
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ef9ed2ccbc
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added duplicate_grid_pin test case
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2019-12-26 15:08:31 -07:00 |
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AurelienUoU
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32176eb352
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Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
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tangxifan
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96733f9ea8
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add minor comments in task file for modelsim regression tests
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2019-11-16 22:34:03 -07:00 |
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tangxifan
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a13f406918
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tweaking mcnc_big20 task run for modelsim
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2019-11-16 18:00:55 -07:00 |
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tangxifan
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4df6402241
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add python script for batch simulations
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2019-11-15 14:23:03 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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00280b835e
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reorganize regression tests
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2019-11-05 16:31:42 -07:00 |
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tangxifan
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7952d134b9
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add tree-like mux test case to regression test
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2019-11-05 16:24:39 -07:00 |
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tangxifan
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0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
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dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |
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tangxifan
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49bfb3223c
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add compact routing to regression test
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2019-11-01 10:53:47 -06:00 |
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tangxifan
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531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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tangxifan
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d709868463
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adding more regression tests which is quick run but very helpful for debugging
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2019-10-31 20:17:40 -06:00 |
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tangxifan
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a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
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tangxifan
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5531422186
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update regression test with no-explicit port mapping cases
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2019-10-30 19:37:06 -06:00 |
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tangxifan
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55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
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10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
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5cb3717433
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add single mode test case to regression test. debugging now
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2019-10-28 15:57:17 -06:00 |
Baudouin Chauviere
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027272c976
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Faster regression test
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2019-10-05 12:10:55 -06:00 |
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Baudouin Chauviere
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db059af8b8
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Lighten the regression test
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2019-10-03 13:33:28 -06:00 |
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Baudouin Chauviere
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c7e1f7d90b
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Added explicit_verilog to regression test in a clean way
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2019-10-03 10:17:04 -06:00 |
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Baudouin Chauviere
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33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
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Baudouin Chauviere
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7c3ab38410
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Hot fix
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2019-10-01 16:40:16 -06:00 |
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AurelienUoU
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feddcbcb21
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-23 11:41:38 -06:00 |
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tangxifan
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5efea159c5
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Simplify part of regression test to min_route_chan_width
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2019-09-22 11:14:33 -06:00 |
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AurelienUoU
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cc0bfdd548
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Add testcase in regression test for architecture with 1 IO cell/IO block
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2019-09-20 10:27:26 -06:00 |
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tangxifan
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4e7af5cdc5
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update tileable_routing test
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2019-09-18 15:59:32 -06:00 |
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tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
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5abbfd6a0f
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add tileable routing to regression test
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2019-09-16 20:45:02 -06:00 |
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tangxifan
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f04565386f
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refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
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de8a6bc833
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update regression tests
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2019-08-26 21:00:15 -06:00 |
Ganesh Gore
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7a3ff94116
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Added blif task in travis script
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2019-08-25 01:28:21 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
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Ganesh Gore
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89589ddc1c
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-22 18:46:51 -06:00 |
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Ganesh Gore
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2f0acfad23
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Updated travis to run regression task
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2019-08-21 11:09:53 -06:00 |
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tangxifan
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59f1ac7310
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add missing files and try to refactor submodule essential
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2019-08-20 20:49:26 -06:00 |
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tangxifan
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5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
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60e8d2b29f
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add missing files and try to refactor submodule essential
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2019-08-20 16:13:08 -06:00 |
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Ganesh Gore
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8d0153d34e
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Added gitignore to skip run directory tracking
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2019-08-19 19:06:01 -06:00 |
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Ganesh Gore
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901932a4fc
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First draft: Working openfpga task flow
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2019-08-16 09:44:50 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |