tangxifan
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907308ee0f
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[Doc] Update bitstream distribution file format
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2022-03-29 20:09:24 +08:00 |
taoli4rs
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781250f0bb
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Fix a small typo to trigger the CI flow.
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2022-03-22 16:36:45 -07:00 |
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tangxifan
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6ff69d26b9
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[Doc] An example to the documentation about the new feature in tile_annotation
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2022-03-20 13:12:13 +08:00 |
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tangxifan
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123bb70cb3
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[Doc] More explanantion on the use of config_enable attribute for circuit ports
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2022-02-23 15:53:58 -08:00 |
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tangxifan
|
b78e58d9bf
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[Doc] Update doc about big endian syntax in bus group file format
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2022-02-18 23:07:18 -08:00 |
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tangxifan
|
8116141210
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[Doc] Update documentation on the bus group feature
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2022-02-18 15:46:25 -08:00 |
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tangxifan
|
37d8617a5c
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[Doc] Update due to new options
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2022-02-17 19:45:37 -08:00 |
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tangxifan
|
4a78bcf5d3
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[Doc] update file format about bus group
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2022-02-17 15:15:05 -08:00 |
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tangxifan
|
796428d848
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[Doc] Add documentation about bus group file format
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2022-02-17 14:22:21 -08:00 |
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tangxifan
|
2b5fded2a9
|
[Doc] Update documentation on the new option
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2022-02-01 13:25:58 -08:00 |
|
tangxifan
|
b7b0a2a5d8
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[Doc] Update doc about the new option
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2022-02-01 12:19:26 -08:00 |
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tangxifan
|
63f44adf15
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[FPGA-Verilog] Now have a new option ``--use_relative_path``
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2022-01-31 12:48:05 -08:00 |
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tangxifan
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a9a56686e2
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[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
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2022-01-26 11:10:29 -08:00 |
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tangxifan
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25143d07f1
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[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
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2022-01-25 13:37:54 -08:00 |
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tangxifan
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a4659020f2
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Merge branch 'master' into time_stamp
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2022-01-25 12:11:35 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
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Aram Kostanyan
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2b008177e7
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Updated documentation.
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2022-01-17 14:58:20 +05:00 |
Awais Abbas
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54d4f30592
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OpenFPGA Documentation updated for yosys only support
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2022-01-14 16:14:48 +05:00 |
nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
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a355977420
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Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
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tangxifan
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57159fc121
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[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
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2021-10-10 17:46:45 -07:00 |
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tangxifan
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40b589dc6d
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[Doc] Update documentation about the clock definition for programming clocks in simulation settings
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2021-10-06 13:50:33 -07:00 |
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tangxifan
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03bcf6dee5
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[Doc] Update documenation for the new option ``--keep_dont_care_bits``
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2021-10-05 19:23:42 -07:00 |
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tangxifan
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ff339312f6
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[Doc] Update documentation about the limitations of multi-region configuration protocols
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2021-10-05 11:55:10 -07:00 |
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tangxifan
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9a7e0f761a
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[Doc] Add fabric bitstream file format for QL memory bank
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2021-10-04 12:29:49 -07:00 |
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tangxifan
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a01fa7c282
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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tangxifan
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b0a97a7052
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[Doc] Update doc about WLR usage for QL memory bank
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2021-09-27 10:24:04 -07:00 |
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tangxifan
|
f9bceff33a
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[Doc] Update documentation for the flatten BL/WL protocols
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2021-09-25 20:44:45 -07:00 |
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tangxifan
|
10774dc15c
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[Doc] Updated documentation about new syntax in fabric key
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2021-09-21 17:01:52 -07:00 |
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tangxifan
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d9d959709c
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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tangxifan
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3146d2484f
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[Doc] Update documentation on the WLR definition for circuit model
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2021-09-20 17:21:33 -07:00 |
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tangxifan
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73d21c9730
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[Doc] Update doc about how to use the QuickLogic memory bank
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2021-09-10 15:30:37 -07:00 |
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tangxifan
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43afaca17c
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[Doc] Add more details about the new syntax
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2021-07-01 23:51:54 -06:00 |
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tangxifan
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0851075bc9
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[Doc] Update documentation about the new feature in pin constraint file
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2021-07-01 23:47:36 -06:00 |
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tangxifan
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ac9046b7d2
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[Doc] Remove ``define_simulation.v`` since it is no longer needed.
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2021-06-29 15:38:35 -06:00 |
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tangxifan
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30027b8c15
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[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
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2021-06-25 15:27:15 -06:00 |
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tangxifan
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11d0283771
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[Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream'
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2021-06-25 15:11:12 -06:00 |
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tangxifan
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507f5ee54c
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[Doc] Update documentation about time unit support in writing simulation file
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2021-06-25 10:34:43 -06:00 |
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tangxifan
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8e2ba718d0
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[Doc] update documentation on the new option '--testbench_type'
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2021-06-25 10:16:48 -06:00 |
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tangxifan
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779437cd37
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[Doc] Update documentation to remove out-of-date options related to signal_init
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2021-06-24 17:07:15 -06:00 |
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tangxifan
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9585e1d3b5
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[Doc] Update documentation about 'default_net_type' option in testbench generators
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2021-06-14 14:00:34 -06:00 |
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tangxifan
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b719419931
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[Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command
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2021-06-09 16:59:02 -06:00 |
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tangxifan
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54a53bc988
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[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol
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2021-06-07 17:58:00 -06:00 |
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tangxifan
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0fee741008
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[Doc] Update documentation on the minor changes on fabric bitstream file format
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2021-06-07 14:22:35 -06:00 |
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tangxifan
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c30be6e95e
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[Doc] Update documentation about the fast configuration for write bitstream command
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2021-06-04 20:00:28 -06:00 |
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tangxifan
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059e74b4ef
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[Doc] Add --fast configuration option to documentation for 'write_full_testbench'
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2021-06-04 15:17:00 -06:00 |
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tangxifan
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b83d8826fb
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[Doc] Update documentation on the testbench organization/waveforms
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2021-06-03 16:54:13 -06:00 |
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tangxifan
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9bcaa820ae
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[Doc] Update documentation for the new command 'write_full_testbench'
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2021-06-03 16:18:07 -06:00 |
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tangxifan
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9b40e74e25
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[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
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2021-05-24 15:24:50 -06:00 |
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tangxifan
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21a18069a1
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[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
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2021-05-24 14:50:55 -06:00 |
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tangxifan
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b6b98a75b8
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[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
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2021-05-24 13:03:40 -06:00 |
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tangxifan
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24f83f0058
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[Doc] Update documentation about the new command 'report_bitstream_distribution'
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2021-05-07 11:54:33 -06:00 |
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tangxifan
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1bae59dc6a
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[Doc] Update documentation for the write_io_mapping command
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2021-04-27 14:54:57 -06:00 |
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tangxifan
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62dc5a3856
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[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
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2021-04-24 16:02:24 -06:00 |
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tangxifan
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2e1cc5499d
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[Doc] Add disclaimer for limitations when using repack pin constraints
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2021-04-21 14:14:54 -06:00 |
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tangxifan
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9b3dcc65bd
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[Doc] Add new bitstream setting syntex 'interconnect' to documentation
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2021-04-19 16:37:21 -06:00 |
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tangxifan
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e5b47b7d3d
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[Doc] Update documentation on the changes on fabric bitstream file formats
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2021-04-10 15:45:39 -06:00 |
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tangxifan
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19b2641839
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Merge branch 'master' into doc_patch
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2021-03-15 11:45:32 -06:00 |
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tangxifan
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fb7d76545e
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[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
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2021-03-15 11:40:09 -06:00 |
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tangxifan
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ff0faeb285
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[Doc] Update documentation about the extended bitstream setting
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2021-03-10 21:41:59 -07:00 |
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tangxifan
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c638e5bde5
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[Doc] Update documentation for default net type option
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2021-02-28 12:00:55 -07:00 |
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tangxifan
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01b9bf2a02
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[Doc] Update num_region XML for config protocol
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2021-02-18 21:58:30 -07:00 |
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tangxifan
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1c4dc9f74b
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[Doc] Update documentation about the super LUT feature
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2021-02-10 11:49:59 -07:00 |
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tangxifan
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9c5368f912
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[Doc] Correct bugs in compiling latexpdf
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2021-02-07 16:17:54 -07:00 |
AurelienAlacchi
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00fc3d7622
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Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
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2021-02-05 09:53:28 -07:00 |
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tangxifan
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9b5c64f35f
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[Doc] Update documentation about disable_packing syntax
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2021-02-04 16:41:24 -07:00 |
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tangxifan
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d83158654c
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[Doc] Add a draft documentation about the bitstream setting
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2021-02-01 22:33:17 -07:00 |
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tangxifan
|
0e16638dc2
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[Doc] Update documentation about the changes on activity files
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2021-01-29 11:49:07 -07:00 |
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tangxifan
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78ad9cd000
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[Doc] Add version command/option to documentation
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2021-01-27 16:06:45 -07:00 |
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tangxifan
|
d53d3963d4
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[Doc] Broken link fix in config protocol documentation
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2021-01-26 14:05:11 -07:00 |
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tangxifan
|
9fefe1502f
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[Doc] Typo fix on write_fabric_key option
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2021-01-25 15:18:16 -07:00 |
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tangxifan
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dd0680246a
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[Doc] Typo fix on fabric key command
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2021-01-25 14:12:40 -07:00 |
ganeshgore
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1ba7e0663f
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Merge pull request #176 from lnis-uofu/dev
Documentation Formatting
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2021-01-24 21:11:49 -07:00 |
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tangxifan
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e18c533657
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[Doc] Add new openfpga shell command to documentation
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2021-01-24 14:48:56 -07:00 |
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tangxifan
|
815468ac65
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[Doc] Add shortcut to call pin constraint option to documentation
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2021-01-20 09:20:51 -07:00 |
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tangxifan
|
977ff52cb1
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[Doc] Format openfpga command documentation by using option views
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2021-01-19 20:26:38 -07:00 |
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tangxifan
|
e9dc708d66
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[Doc] Group file format documentation into a unified section
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2021-01-19 19:44:44 -07:00 |
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tangxifan
|
ac8c63553a
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[Doc] Add file format index file
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2021-01-19 18:07:53 -07:00 |
|
tangxifan
|
fbb5c0cf8f
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[Doc] Add pin constraints to documentation
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2021-01-19 18:04:45 -07:00 |
|
tangxifan
|
c7f02601ab
|
[Doc] Add repack design constraints to documentation
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2021-01-17 12:59:46 -07:00 |
|
tangxifan
|
c4d3e7c50c
|
[Doc] Update documentation for the new XML syntax in simulation settings
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2021-01-15 12:30:26 -07:00 |
|
tangxifan
|
0c808bec41
|
[Doc] Add clarification for defining multi-bit global tile ports
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2021-01-09 20:00:16 -07:00 |
|
tangxifan
|
2324edc522
|
[Doc] Update documentation for upgraded tile annotation
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2021-01-09 18:55:16 -07:00 |
|
tangxifan
|
226f6b8d6d
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
|
tangxifan
|
406edeec89
|
[Doc] Typo fix
|
2020-12-04 15:07:02 -07:00 |
|
tangxifan
|
4fe190fa7e
|
[Doc] Bug fix in LUT circuit model documentation
|
2020-12-04 14:44:27 -07:00 |
|
tangxifan
|
8350b0f911
|
[Doc] Update documentation about default value definition in tile annotation
|
2020-12-02 17:08:34 -07:00 |
|
tangxifan
|
cc0114459a
|
[Doc] Enrich examples for LUT circuit models
|
2020-11-26 13:03:12 -07:00 |
|
tangxifan
|
62e804215b
|
[Doc] Add svg figures for LUT examples
|
2020-11-26 12:35:39 -07:00 |
|
tangxifan
|
b857135f4e
|
[Doc] Add clarification about which cells are applicable for signal initialization
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2020-11-23 15:19:15 -07:00 |
|
tangxifan
|
2b9a97729e
|
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
|
2020-11-23 15:09:47 -07:00 |
|
tangxifan
|
fd0e6814ea
|
[Doc] Update documentation about the pre-processing flags
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2020-11-22 20:33:15 -07:00 |
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tangxifan
|
f6126d1ed6
|
[Doc] Add illustrative example to diff between global ports definitions
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2020-11-12 09:24:39 -07:00 |
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tangxifan
|
bc43c876b0
|
[Doc] Update documentation for the rules in global port definition for tile ports
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2020-11-11 14:10:11 -07:00 |
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tangxifan
|
2c269c532a
|
[Doc] Update doc for the global port definition using physical tile port
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2020-11-10 20:48:28 -07:00 |
|
tangxifan
|
056b7c0c79
|
[Doc] Update documentation about CCFF circuit model examples
|
2020-11-06 12:22:22 -07:00 |