Commit Graph

65 Commits

Author SHA1 Message Date
Baudouin Chauviere 31c3eba111 ReadMe modifications to add the beginning of the FPGA-SPICE tutorial
Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial
2018-09-27 09:33:39 -06:00
Baudouin Chauviere 16c0c4656e Adds titles and WiP tags for new parts. Tutorials included
Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
2018-09-25 14:53:04 -06:00
Baudouin Chauviere 70d303dfb5 Define Circuit doc improvement
Added some content, better spacing for understanding and made some changes in the options we show
2018-09-25 11:53:53 -06:00
tangxifan 681cca99a4 fix a bug in tapbuf 2018-09-21 19:00:22 -06:00
tangxifan d683134b12 rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
tangxifan 6461279a80 fixing minor bugs 2018-09-17 11:25:54 -06:00
tangxifan f47246e8b7 Fixed doc ref problem 2018-09-14 14:02:47 -06:00
tangxifan 087ba475bb debugging bibtex 2018-09-14 13:58:20 -06:00
tangxifan 965835debe debugging doc ref 2018-09-14 13:48:57 -06:00
tangxifan 4afbce10a3 fixing bugs for doc references 2018-09-14 13:44:40 -06:00
tangxifan 5d697da4e7 refine doc hierarchy 2018-09-14 13:27:05 -06:00
Xifan Tang c7783575d9 Clean codes 2018-09-14 13:16:26 -06:00
唐希凡 0bfbc9b0aa update docs 2018-09-14 13:11:51 -06:00
Xifan Tang 44e63ec98b Test new template 2018-09-13 23:00:56 -06:00
Xifan Tang fec0daa2a8 Update a draft 2018-09-13 22:58:54 -06:00
唐希凡 0f31d51c1a update doc html template 2018-09-13 17:59:53 -06:00
唐希凡 655baa3cd9 Debugged Doc 2018-09-13 17:39:57 -06:00
Xifan Tang cea41801da updating documentation 2018-09-13 16:25:24 -06:00
Xifan Tang c94cc01c83 debugging documentation 2018-09-13 15:52:08 -06:00
Xifan Tang 7261a53f3c update docs theme 2018-09-13 15:48:10 -06:00
Xifan Tang d6d6951496 Adding documentation 2018-09-13 15:38:41 -06:00
Xifan Tang d7e2a78d86 creating documentation 2018-09-13 11:52:12 -06:00
Xifan Tang bdffcbd559 creating documentations 2018-09-13 11:51:32 -06:00
Xifan Tang 1cf066d3ad Fixing minor bugs 2018-09-06 14:25:23 -06:00
Xifan Tang c009a37580 fix minor bugs 2018-09-04 17:56:37 -06:00
Xifan Tang 42da9160f0 Clean codes and update 2018-09-04 17:49:20 -06:00
Xifan Tang 9f3cb45b85 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-09-04 17:33:38 -06:00
Xifan Tang 00ecd0bb1d Cleanup codes and organization 2018-09-04 17:31:30 -06:00
tangxifan d3d95ee842
Update getting_started.md 2018-08-10 14:17:12 -06:00
Xifan Tang cb15bb5082 Clean code and fix minor bugs 2018-08-10 13:46:00 -06:00
Xifan Tang b0ef554b35 Add power property XML 2018-08-09 11:27:36 -06:00
Xifan Tang 90669d19c5 Update FPGA-SPICE and flow configurations 2018-08-09 11:27:16 -06:00
Xifan Tang 4d7f4350de get FPGA-SPICE updated for release - Clear printf and fix assert bugs 2018-08-01 14:04:28 -06:00
Steve Corey 91f073cdc4 added build files to .gitignore 2018-07-30 10:36:34 -06:00
Xifan Tang fe13168f8f Add ABC and ACE2, fix bugs for fpga_flow and VPR 2018-07-27 22:54:52 -06:00
Steve Corey b9d583519b Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA 2018-07-26 13:59:26 -06:00
Steve Corey be6c296c22 initial commit of black-box doc 2018-07-26 13:58:58 -06:00
Xifan Tang 158dec405e Reorganize the code directory 2018-07-26 11:28:21 -06:00
Steve Corey 3abce69f7c multimode clb simple documentation complete 2018-07-18 10:54:05 -06:00
Steve Corey c61d11baa6 changed some names to make more sense 2018-07-18 10:53:21 -06:00
Steve Corey 9c4e5ca95f ignored vpr output files 2018-07-18 10:50:37 -06:00
Steve Corey 1b36d491c8 ignored vpr output files 2018-07-18 10:48:55 -06:00
Steve Corey 51efa38751 continuing simple documentation 2018-07-17 13:55:10 -06:00
Steve Corey 84fd0348af initial commit of simple architecture documentation 2018-07-16 13:22:18 -06:00
Steve Corey 6f73b7a874 moved architecture documentation to new file 2018-07-16 13:21:41 -06:00
Steve Corey 17988e2ade changed switch names to make more sense 2018-07-16 13:21:07 -06:00
Steve Corey fa50eef093 added simple architecture for vpr version 8 2018-07-11 13:19:40 -06:00
Steve Corey 2208916a95 updated to line numbers of vpr8 example architecture 2018-07-10 13:02:21 -06:00
Steve Corey 8040328841 added notes about CLB 2018-07-09 13:06:22 -06:00
Steve Corey 8c7a7af458 started documenting architecture 2018-07-06 13:36:55 -06:00