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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 8cbea6a268 [HDL] Add technology library for customizable DFF synthesis 2021-04-21 19:50:51 -06:00
tangxifan ff4460695b [HDL] Add dff tech map files for yosys 2021-04-16 17:00:55 -06:00