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OpenFPGA
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5495 Commits

Author SHA1 Message Date
tangxifan 8272d2dcbc [engine] enrich verbose output for repacker, easier to debug 2022-09-27 10:46:57 -07:00
tangxifan 48c9090514
Merge branch 'master' into dependabot/submodules/yosys-plugins-27208ce 2022-09-27 09:46:11 -07:00
tangxifan 56018b87b1
Merge pull request #810 from lnis-uofu/cmake_options 
Options to compile the codebase partially
 2022-09-27 09:45:59 -07:00
dependabot[bot] e7c3ee1f59
Bump yosys-plugins from `0713ed7` to `27208ce` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `0713ed7` to `27208ce`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](0713ed79ab...27208ce082)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-09-27 06:17:27 +00:00
tangxifan 7fcaecd0f5 [script] enable abc build in vtr because we need ace2 2022-09-26 21:06:51 -07:00
tangxifan 9b65472ffb [doc] update compilation guidelines 2022-09-26 16:22:40 -07:00
tangxifan 445a24535a [ci] typo 2022-09-26 16:13:00 -07:00
tangxifan 76404d6b81 [ci] add missing quotes 2022-09-26 16:03:32 -07:00
tangxifan c1665bb26c [ci] deploy new build tests to ci 2022-09-26 15:58:10 -07:00
tangxifan 820b5ea5bf [script] add options to cmake: users can skip the build of Yosys, yosys-plugin, and testing; Force to turn off building abc, odin and yosys in vtr 2022-09-26 15:46:12 -07:00
tangxifan 8e817287ae
Merge pull request #808 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-09-23 17:14:45 -07:00
github-actions[bot] d3e8f1eb80 Updated Patch Count 2022-09-24 00:04:00 +00:00
tangxifan 016b85ed7a
Merge pull request #806 from lnis-uofu/ganesh_dev 
Updated readme, breaking changes in v1.2, and instruction to use v1.1
 2022-09-23 10:20:49 -07:00
Ganesh Gore 0aacaa9eea Updated readme 2022-09-23 11:08:44 -06:00
Ganesh 66555df2c8 Updated readme 
+ Tagged fianl build of v1.1 as Final1.1
+ Instruction to access last build of v1.1
+ Added instructions for arch file upgrade
 2022-09-23 10:10:22 -06:00
tangxifan 62ec82c18d
Merge pull request #805 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-09-21 21:58:26 -07:00
github-actions[bot] 87e9454aad Updated Patch Count 2022-09-22 04:53:12 +00:00
tangxifan 6511983617
Update patch_updater.yml 2022-09-21 21:52:23 -07:00
tangxifan afde3eaa65
Update patch_updater.yml 2022-09-21 21:29:52 -07:00
tangxifan d7fb6d9547
Merge pull request #747 from lnis-uofu/vtr_upgrade 
Now use latest VTR as a submodule
 2022-09-21 21:25:07 -07:00
tangxifan 8ee3fb879f
Update VERSION.md 2022-09-21 21:16:20 -07:00
tangxifan d543a8661f
Merge branch 'master' into vtr_upgrade 2022-09-21 19:08:50 -07:00
tangxifan 88cffb4b39
Merge pull request #802 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-09-21 17:06:26 -07:00
github-actions[bot] 62e91c1dab Updated Patch Count 2022-09-22 00:03:28 +00:00
tangxifan 79b260f5e1 [arch] update missing arch 2022-09-21 16:52:32 -07:00
tangxifan b1f8cdab3c [test] update missing arch files which are not placed in the openfpga_flow/vpr_arch 2022-09-21 15:28:56 -07:00
tangxifan eaa0b5588a [test] fixed a bug in pin constrain examples 2022-09-21 14:10:12 -07:00
tangxifan b532bca9d2 [script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment 2022-09-21 10:54:16 -07:00
tangxifan baac236ed7 [test] fixed a bug in example scripts due to the changes on vpr options 2022-09-21 10:52:49 -07:00
tangxifan d0b018ad6e [script] mismatches in vpr options due to upgrade 2022-09-21 09:27:26 -07:00
tangxifan 40edf859e3 Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-20 22:38:06 -07:00
tangxifan 97f0445787 [arch] upgrade arch file which was designed for v1.1 2022-09-20 22:37:35 -07:00
tangxifan 36603f9772
Merge branch 'master' into vtr_upgrade 2022-09-20 21:08:06 -07:00
tangxifan 1354a4bfa8
Merge pull request #800 from lnis-uofu/reg_hotfix 
[test] Now git diff in basic regression tests should capture the changes on golden outputs
 2022-09-20 20:53:47 -07:00
tangxifan e0f632cc9c [test] fixed a bug 2022-09-20 20:29:34 -07:00
tangxifan 645d8df7b9 [test] fixed a bug 2022-09-20 20:09:41 -07:00
tangxifan 9042fc2422 [test] now reg test should show diff details when failed 2022-09-20 19:32:34 -07:00
tangxifan b8f1520367 [test] fixed a bug 2022-09-20 18:12:23 -07:00
tangxifan 4e254a304d [test] now golden netlists have no relationship with OPENFPGA_PATH 2022-09-20 18:10:52 -07:00
tangxifan 5e23be19a5 [test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths 2022-09-20 18:07:31 -07:00
tangxifan 1b0b50b928 [test] update golden netlist 2022-09-20 16:04:05 -07:00
tangxifan a137f7148c [arch] fixed a bug 2022-09-20 15:47:15 -07:00
tangxifan da157ed5de [test] debugging git-diff 2022-09-20 15:31:39 -07:00
tangxifan 3f8106f12e [arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric 2022-09-20 15:19:32 -07:00
tangxifan b630d60b7e [test] update arch bitstream and force a pin placement for the test case where external bistream is fixed 2022-09-20 14:14:18 -07:00
tangxifan 6a896a9845 [test] debugging 2022-09-20 14:08:22 -07:00
tangxifan ecfdc4a83a [test] debugging 2022-09-20 13:51:32 -07:00
tangxifan abee802830 [script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers 2022-09-20 13:46:30 -07:00
tangxifan bdcdc7d294 [test] Now git diff in basic regression tests should capture the changes on golden outputs 2022-09-20 13:36:31 -07:00
tangxifan 37c5056d6a [test] now use a fixed routing channel width for quicklogic tests 2022-09-20 12:25:40 -07:00