tangxifan
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8b00bfdff9
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[test] replace hardcoded paths in task config files with relative paths
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2022-10-17 11:55:57 -07:00 |
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tangxifan
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aa78981e37
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[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
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2022-10-17 11:18:21 -07:00 |
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tangxifan
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e9ee039e60
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Merge branch 'master' into rst_on_lut_strong
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2022-10-13 16:01:57 -07:00 |
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tangxifan
|
33e2b16cb1
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[arch] fixed a bug which caused verification failed
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2022-10-13 15:33:43 -07:00 |
|
tangxifan
|
1c36ac28f1
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[arch] code format
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2022-10-13 12:17:32 -07:00 |
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tangxifan
|
32f48f16c7
|
[arch] fixed a few bugs
|
2022-10-13 11:54:58 -07:00 |
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tangxifan
|
b0be27b384
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[test] add repack design constraints files
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2022-10-13 11:22:48 -07:00 |
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tangxifan
|
5cf315958d
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[test] deploy new test to basic regression tests
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2022-10-13 11:17:34 -07:00 |
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tangxifan
|
7b7217d116
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[arch]add new arch to test
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2022-10-13 11:08:51 -07:00 |
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tangxifan
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7f67794787
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[arch]add new arch to test
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2022-10-13 10:54:40 -07:00 |
mustafa.arslan
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d7a253408d
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Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
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2022-10-13 14:00:59 +03:00 |
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mustafa.arslan
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6f55371d4b
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Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
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2022-10-13 13:53:32 +03:00 |
Yunus Emre ERYILMAZ
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f62d435b1e
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Update frac_mem_32k.v
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2022-10-12 09:35:35 +03:00 |
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tangxifan
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35869b480a
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Merge branch 'master' into xmllint
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2022-10-07 10:47:43 -07:00 |
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tangxifan
|
85089cbc88
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[arch] apply xml format for all the architecture files
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2022-10-07 10:31:51 -07:00 |
|
mustafa.arslan
|
508c01cef6
|
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
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2022-10-07 09:38:07 +03:00 |
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tangxifan
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ab53f88c2b
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[test] now use a fixed device layout for the single-mode LUT design testcase
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2022-10-04 10:05:22 -07:00 |
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tangxifan
|
13c819bb28
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[ci] deply new test to ci
|
2022-10-01 11:04:08 -07:00 |
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tangxifan
|
4eaecde0b9
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[test] add golden netlists to ensure no cout in gsb
|
2022-10-01 11:03:13 -07:00 |
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tangxifan
|
78f30cf072
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[test] add a new test to track the golden netlists where cout is not in GSB
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2022-09-30 15:38:27 -07:00 |
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tangxifan
|
0d8d8446ee
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[test] fixed a bug where OPIN for direct connection is included in GSB
|
2022-09-30 15:24:51 -07:00 |
|
tangxifan
|
088ff1a474
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[script] fixed a bug
|
2022-09-29 16:27:03 -07:00 |
|
tangxifan
|
0565ca7aca
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[script] add missing files
|
2022-09-29 16:14:38 -07:00 |
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tangxifan
|
a3e7133d63
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Merge branch 'master' into wire_lut_test
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2022-09-29 16:02:18 -07:00 |
|
tangxifan
|
2ed4a60f36
|
[arch] reduce clb inputs to force net remapping during routing
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2022-09-29 15:52:30 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
9bc9b61d35
|
[test] fixed a few bugs
|
2022-09-29 15:11:30 -07:00 |
|
tangxifan
|
f5e7ec4dd1
|
[test] add a new test case to validate wire lut case
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2022-09-29 14:28:59 -07:00 |
|
tangxifan
|
df1ae7ba2a
|
[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker
|
2022-09-29 14:23:17 -07:00 |
|
tangxifan
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f7a02422b5
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[arch] add a new arch to reproduce the wire-lut bug in repacker
|
2022-09-29 13:59:08 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
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49fa783914
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[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
79b260f5e1
|
[arch] update missing arch
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2022-09-21 16:52:32 -07:00 |
|
tangxifan
|
b1f8cdab3c
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[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
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2022-09-21 15:28:56 -07:00 |
|
tangxifan
|
eaa0b5588a
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[test] fixed a bug in pin constrain examples
|
2022-09-21 14:10:12 -07:00 |
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tangxifan
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b532bca9d2
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[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
|
2022-09-21 10:54:16 -07:00 |
|
tangxifan
|
baac236ed7
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[test] fixed a bug in example scripts due to the changes on vpr options
|
2022-09-21 10:52:49 -07:00 |
|
tangxifan
|
d0b018ad6e
|
[script] mismatches in vpr options due to upgrade
|
2022-09-21 09:27:26 -07:00 |
|
tangxifan
|
40edf859e3
|
Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-20 22:38:06 -07:00 |
|
tangxifan
|
97f0445787
|
[arch] upgrade arch file which was designed for v1.1
|
2022-09-20 22:37:35 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
e0f632cc9c
|
[test] fixed a bug
|
2022-09-20 20:29:34 -07:00 |
|
tangxifan
|
645d8df7b9
|
[test] fixed a bug
|
2022-09-20 20:09:41 -07:00 |
|
tangxifan
|
9042fc2422
|
[test] now reg test should show diff details when failed
|
2022-09-20 19:32:34 -07:00 |
|
tangxifan
|
b8f1520367
|
[test] fixed a bug
|
2022-09-20 18:12:23 -07:00 |
|
tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
|
2022-09-20 18:10:52 -07:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
1b0b50b928
|
[test] update golden netlist
|
2022-09-20 16:04:05 -07:00 |
|
tangxifan
|
a137f7148c
|
[arch] fixed a bug
|
2022-09-20 15:47:15 -07:00 |
|
tangxifan
|
da157ed5de
|
[test] debugging git-diff
|
2022-09-20 15:31:39 -07:00 |