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OpenFPGA
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715 Commits

Author SHA1 Message Date
tangxifan 366dcff75d [Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol 2021-06-07 21:49:31 -06:00
tangxifan 9808b61b36 [Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases 2021-06-07 20:06:39 -06:00
tangxifan ba75c18378 [Tool] Now 'write_full_testbench' supports memory bank configuration protocol 2021-06-07 17:40:07 -06:00
tangxifan 1a5902ca74 [Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled 2021-06-07 14:32:56 -06:00
tangxifan af298de121 [Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol 2021-06-07 13:53:32 -06:00
tangxifan d644b8f22d [Tool] Support external bitstream file when generating full testbench for frame-based decoder 2021-06-07 11:55:11 -06:00
tangxifan 618b04568f [Tool] Remove unnecessary new line in bitstream file 2021-06-04 20:07:42 -06:00
tangxifan cf7addb1a6 [Tool] Add heads to bitstream plain text file 2021-06-04 19:48:48 -06:00
tangxifan 70fb3a85dc [Tool] Patch fast configuration in bitstream writing 2021-06-04 17:23:10 -06:00
tangxifan d98be9f87b [Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog 2021-06-04 16:45:00 -06:00
tangxifan 6e69c2d70a [Tool] Patch fast configuration in full Verilog testbench generator 2021-06-04 16:34:55 -06:00
tangxifan 061f832429 [Tool] Enable fast configuration when writing fabric bitstream 2021-06-04 16:23:40 -06:00
tangxifan 81048d3698 [Tool] Add option '--fast_configuration' to 'write_full_testbench' command 2021-06-04 11:26:39 -06:00
tangxifan 98308133c1 [Tool] Add configuration skip capability to top testbench which loads external bitstream file 2021-06-04 11:24:05 -06:00
tangxifan adb18d28b8 [Tool] Remove unused arguments 2021-06-04 10:37:28 -06:00
tangxifan 67485269d3
Merge branch 'master' into testbench_external_bitstream 2021-06-03 15:46:25 -06:00
tangxifan ae6a46cd60 [Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique 2021-06-03 15:41:11 -06:00
tangxifan 1fd399736d [Tool] Patch FPGA-SDC to consider time unit in global port timing constraints 2021-05-27 10:26:20 -06:00
tangxifan c4ecc9ee7c [Tool] Patch data type of report bitstream distribution command-line option 2021-05-07 11:44:01 -06:00
tangxifan db9bb9124e [Tool] Add report bitstream distribution command to openfpga shell 2021-05-07 11:41:25 -06:00
tangxifan 8728fd9561 [Tool] Typo fix to resolve clang errors 2021-04-27 15:06:07 -06:00
tangxifan c5d36757c6 [Tool] Fix typo in io mapping writing 2021-04-27 14:39:57 -06:00
tangxifan 43c1e052ef [Tool] Add a writer to output I/O mapping information to XML files 2021-04-27 14:30:16 -06:00
tangxifan 148da80869 [Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes 2021-04-24 14:53:29 -06:00
tangxifan 0709e5bb81 [Tool] Fixed a bug in the routing trace finder for direct connections inside repacker 2021-04-24 13:27:44 -06:00
tangxifan 56948244bc [Tool] Patch a critical bug in pb pin fixup 2021-04-22 16:19:54 -06:00
tangxifan 96ce6b545f [Tool] Patch repack to consider design constraints for pins that are not equivalent 2021-04-21 13:53:08 -06:00
tangxifan 0aec30bac6 [Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file 2021-04-19 15:53:33 -06:00
tangxifan 0b49c22682 [Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks 2021-04-18 16:11:11 -06:00
tangxifan 6550ea3dfa [Tool] Rework pin constarint API to avoid expose raw data to judge for developers 2021-04-18 12:02:49 -06:00
tangxifan 6e9b24f9bf [Tool] Patch the invalid pin constraint net name 2021-04-17 19:56:30 -06:00
tangxifan 253422e7b7 [Tool] Bugfix due to refactoring 2021-04-17 19:27:03 -06:00
tangxifan 02ca51d84b [Tool] Reorganize functions in full testbench generator to avoid big-chunk codes 2021-04-17 17:45:50 -06:00
tangxifan d95a1e2776 [Tool] Encapulate search function in PinConstraint data structure 2021-04-17 17:31:55 -06:00
tangxifan da619fabe7 [Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench 2021-04-17 17:19:34 -06:00
tangxifan 6e1b58f8a6 [Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports 2021-04-17 15:05:22 -06:00
tangxifan 7c6e000be8 [Tool] bug fix 2021-04-10 15:36:02 -06:00
tangxifan 03b68a1fdd [Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions 2021-04-10 15:25:39 -06:00
tangxifan 934918d9c0 [Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions 2021-04-10 15:06:53 -06:00
tangxifan 4b8f5f294a [Tool] Capsulate fabric bitstream organization for configuration chain 2021-04-10 14:28:31 -06:00
tangxifan afa0e751da [Tool] Use alias for complex bitstream data types 2021-04-10 14:12:02 -06:00
tangxifan 902c4cf9e9
Merge branch 'master' into dev 2021-03-18 15:14:14 -06:00
tangxifan 3ef292bdbb Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch 2021-03-17 20:28:40 -06:00
tangxifan fa11410425 [Tool] Remove exceptions on outputing verilog port with lsb=0 2021-03-17 20:27:08 -06:00
tangxifan 62a846197b
Merge branch 'master' into dev 2021-03-15 10:06:34 -06:00
tangxifan 87006e1374
Merge branch 'master' into netlist_name_patch 2021-03-15 10:06:24 -06:00
tangxifan 024aa5cbe4
Merge branch 'master' into dev 2021-03-15 09:13:18 -06:00
tangxifan d2fbda4070
Merge branch 'master' into netlist_name_patch 2021-03-15 09:13:04 -06:00
tangxifan b080bcf018
Merge branch 'master' into ganesh_dev 2021-03-15 09:12:50 -06:00
Maciej Kurc 02967f2870 Added writing rr graph node indices to GSB dump. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-03-15 09:28:38 +01:00
tangxifan c8d41b4e69 [Tool] Change routing module port naming to include architecture port names 2021-03-14 19:35:49 -06:00
tangxifan 956b9aca01 [Tool] Trim dead codes in port naming function 2021-03-13 20:23:08 -07:00
tangxifan 2c5634ee76 [Tool] Change pin naming of grid modules to be related to architecture port names 2021-03-13 20:05:18 -07:00
tangxifan 07257d0ff0 [Tool] Patch wrong paths in FPGA-SDC 2021-03-13 10:58:03 -07:00
tangxifan d877a02534 [Tool] Patch the extended bitstream setting support on mode-select bits 2021-03-10 21:28:09 -07:00
tangxifan 85640a7403 [Tool] Extend bitstream setting to support mode bits overload from eblif file 2021-03-10 20:45:48 -07:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
tangxifan 521e1850c8 [Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1 2021-02-28 17:04:27 -07:00
tangxifan 73461971d2 [Tool] Bug fix for printing single-bit ports in Verilog netlists 2021-02-28 16:12:57 -07:00
tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
tangxifan df7b436ac7 [Tool] Patch repacker to support duplicated nets due to adder nets 2021-02-23 19:01:18 -07:00
tangxifan e6091fb3ff [Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition 2021-02-18 21:56:30 -07:00
tangxifan a5b8b2a64a [Tool] Use dedicated function to identify wire LUT created by repacker 2021-02-18 19:37:44 -07:00
tangxifan aae03482f5 [Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database 2021-02-18 19:37:17 -07:00
tangxifan 61012897cd [Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm 2021-02-17 15:31:20 -07:00
tangxifan af4cc117fb [Tool] bug fix in spypad lut 2021-02-09 22:53:18 -07:00
tangxifan 6a0f4f354f [Tool] Support superLUT circuit model in core engine 2021-02-09 20:23:05 -07:00
tangxifan 0c409b5bcc [Tool] Add bitstream annotation support 2021-02-01 20:49:36 -07:00
tangxifan f102e84497 [Tool] Add bitstream setting file to openfpga library 2021-02-01 17:43:46 -07:00
tangxifan 4b77a3a574 [Tool] Now activity file is not a manadatory input of openfpga tools 2021-01-29 11:33:40 -07:00
tangxifan d9fda31a9f [Tool] Add --version to openfpga shell option and a command to openfpga shell 2021-01-27 16:03:46 -07:00
tangxifan fd0e73a9bb [Tool] Enhance return code for openfpga shell 2021-01-24 14:48:27 -07:00
tangxifan 8cac3291cb [Tool] Add batch mode to openfpga shell execution 2021-01-24 14:33:58 -07:00
ganeshgore d502410b40
Merge pull request #179 from lnis-uofu/unused_gpout_patch 
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
 2021-01-23 18:27:54 -07:00
tangxifan 4cc8b08a6c [Tool] Add openfpga version display 2021-01-23 16:38:00 -07:00
tangxifan d2defebee9 [Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches 2021-01-22 16:42:13 -07:00
tangxifan 3f80a26172 [Tool] Bug fix for combinational benchmarks in pre-config testbench generation 2021-01-19 18:22:50 -07:00
tangxifan 75b99b78e9 [Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks 2021-01-19 17:38:51 -07:00
tangxifan da200658c1 [Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks 2021-01-19 17:29:59 -07:00
tangxifan 0670c2de59 [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00
tangxifan 8c311b8282 [Tool] Bug fix in repacker for considering design constraints 2021-01-17 12:26:14 -07:00
tangxifan 2efe513122 [Tool] Now repack consider design constraints; test pending 2021-01-16 21:57:17 -07:00
tangxifan bb8e7e25c2 [Tool] Start deploying design constraints in repack engine 2021-01-16 21:27:12 -07:00
tangxifan fa67517349 [Tool] Add repack design constraints to openfpga command 'repack' 2021-01-16 18:49:34 -07:00
tangxifan ad7a54db1b [Tool] Add repack dc library to compilation 2021-01-16 17:20:59 -07:00
tangxifan 87b2c1f3b8 [Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation 2021-01-15 12:01:53 -07:00
tangxifan 852f5bb72e [Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers 2021-01-14 15:38:24 -07:00
tangxifan 9cc9e45b4b [Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated 2021-01-13 15:13:19 -07:00
tangxifan c0da6b900a [Tool] Bug fix in creating multi-bit clock port connections 2021-01-12 18:38:00 -07:00
tangxifan 65b2fe3ab7 [Tool] Bug fix in the global tile connection by considering all the subtiles 2021-01-10 11:52:38 -07:00
tangxifan 9a441fa5cc [Tool] Upgrade openfpga to support extended global tile port definition 2021-01-09 18:47:12 -07:00
tangxifan cde26597ed [Tool] Bug fix in scan chain builder calling 2021-01-04 18:45:47 -07:00
tangxifan 804b721a19 [Tool] Bug fix in the configuration chain connection builder 2021-01-04 17:41:29 -07:00
tangxifan bfd305b5a5 [Tool] Patch the bug in finding data output ports for CCFF 2021-01-04 17:22:30 -07:00
tangxifan cc91a0aebd [Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder 2021-01-04 17:14:26 -07:00
tangxifan d11a3d9fef [Tool] Avoid outputting signal initialization codes because they are bulky 2020-12-06 14:29:16 -07:00
tangxifan cb2bd2e31c [Tool] Remove register ports for mini local encoders (1-bit data out) 2020-12-06 14:21:54 -07:00
tangxifan 6bdfcb0147 [Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming 2020-12-05 12:44:09 -07:00
tangxifan 6f18688f0e [Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module 2020-12-05 10:53:01 -07:00
tangxifan 0da92ad888 [Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules 2020-12-04 22:16:51 -07:00