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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 2d86a02358 refactored LUT bitstream generation to use vtr logic 2020-02-25 12:45:13 -07:00
tangxifan ed9e038845 add functionality of LUT truth table fix-up 2020-02-06 17:14:29 -07:00