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4065 Commits

Author SHA1 Message Date
tangxifan 223e06d23c
Merge pull request #359 from lnis-uofu/pin_constraint_polarity 
Add Test Cases for the Signal Polarity Support in Pin Constraint Files
 2021-07-02 18:51:24 -06:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan e9d29e27e5 [Tool] Bug fix 2021-07-02 15:32:30 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 6e6c3e9fa4 [Tool] Patch the critical bug in the use of signal polarity in pin constraints 2021-07-02 15:26:21 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
tangxifan a5101be2f6 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 13:58:33 -06:00
tangxifan 2214575a0a
Merge pull request #358 from lnis-uofu/ganesh_dev 
Testcase for benchmark specific variables
 2021-07-02 13:54:07 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
ganeshgore b8bed59ecf
Merge pull request #356 from lnis-uofu/pin_constraint_polarity 
[WIP] Support custom default value in Pin Constraint File
 2021-07-02 10:20:20 -07:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
tangxifan 3906497ef5 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 10:27:40 -06:00
tangxifan f8fb056a42
Merge branch 'master' into pin_constraint_polarity 2021-07-02 10:05:17 -06:00
tangxifan e79da64e95
Merge pull request #354 from lnis-uofu/ganesh_dev 
[Flow] Allows benchmark specific Variable declaration
 2021-07-02 10:05:03 -06:00
tangxifan 43afaca17c [Doc] Add more details about the new syntax 2021-07-01 23:51:54 -06:00
tangxifan 0851075bc9 [Doc] Update documentation about the new feature in pin constraint file 2021-07-01 23:47:36 -06:00
tangxifan 9074bffa68 [Tool] Support customized default value in pin constraint file 2021-07-01 23:43:19 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00
ganeshgore 4818e08448
Merge pull request #327 from lnis-uofu/verilog_testbench 
added configuration benchmark files
 2021-07-01 20:38:16 -07:00
tangxifan b7356d23aa
Merge branch 'master' into verilog_testbench 2021-07-01 21:11:12 -06:00
tangxifan 947f078a7e
Merge pull request #353 from lnis-uofu/testbench_patch 
Bug fix on the reset stimuli generator
 2021-07-01 21:10:40 -06:00
tangxifan d0e4f8521f [Tool] Bug fix on the reset stimuli 2021-07-01 19:58:54 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 006b54c4bc ready for merge 2021-07-01 15:35:39 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
komaljaved-rs be14e4f448 added design_variables.yml 2021-07-01 16:31:42 +05:00
komaljaved-rs 01f79d89b8 Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS 2021-07-01 16:24:12 +05:00
komaljaved-rs ff785569f0 updated ci_test 2021-07-01 16:23:55 +05:00
komaljaved-rs 061811994d
Update ci_test.yml 2021-07-01 16:05:08 +05:00
komaljaved-rs 6d11dc275d
Update ci_test.yml 2021-07-01 16:01:38 +05:00
komaljaved-rs 4b8e178947
Update ci_test.yml 2021-07-01 15:44:59 +05:00
komaljaved-rs 2469f25ef4 updated submodule 2021-07-01 15:14:59 +05:00
komaljaved-rs 7a703659e7 Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS 2021-07-01 15:08:26 +05:00
komaljaved-rs 6559f71082 added ci_scripts 2021-07-01 15:07:37 +05:00
komaljaved-rs 1e81dd897f
Update ci_test.yml 2021-07-01 14:47:59 +05:00