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OpenFPGA
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Commit Graph

191 Commits

Author SHA1 Message Date
tangxifan a98df811ed [Arch] Bug fix: wrong circuit model name was used for CCFF 2021-09-22 15:50:47 -07:00
tangxifan 53da5d49fe [Arch] Correct XML syntax errors 2021-09-22 15:48:14 -07:00
tangxifan 3cfd5c3531 [Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks 2021-09-22 15:04:59 -07:00
tangxifan 212c5bd642 [Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization 2021-09-22 15:04:19 -07:00
tangxifan d0fe12fadd [Arch] Add an example OpenFPGA architecture for 2-region QL memory bank 2021-09-22 10:03:39 -07:00
tangxifan 0450d57d82 [Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR 2021-09-20 16:05:01 -07:00
tangxifan cd2978a434 [Arch] Added a new architecture example which shows how to use the memory bank with readback functionality 2021-09-20 11:13:02 -07:00
tangxifan 6be3c64f1c [Arch] Add an example architecture using the physical design friendly memory bank organization 2021-09-09 09:22:27 -07:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan f77b81fe5b [Arch] recover the mem16k arch as it is used in other test cases 2021-04-28 15:05:30 -06:00
tangxifan 117cea295d [Arch] Patch architecture to be compatible with pin names of DPRAM cell 2021-04-28 11:28:23 -06:00
tangxifan ec4b60f3cc [Arch] Add example arch using 1-kbit DPRAM 2021-04-28 10:47:17 -06:00
tangxifan be98775ae5 [Arch] Reduce the size of DPRAM in example architecture to accelerate testing 2021-04-28 10:45:10 -06:00
tangxifan 834657f2da [Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes 2021-04-27 23:41:14 -06:00
tangxifan 0f8aaae2bc [Arch] Patch architecture using 16kbit dual port RAM 2021-04-27 19:54:34 -06:00
tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition 2021-04-24 14:56:10 -06:00
tangxifan 4f454abfde [Arch] Add a new architecture using fracturable 16-bit DSP blocks 2021-04-24 14:01:42 -06:00
tangxifan ddcdb35b28 [Arch] Bug fix in single-mode 8-bit DSP architectures 2021-04-24 13:30:03 -06:00
tangxifan ce6018e123 [Arch] Enriched DFF model to support active-low/high FFs 2021-04-21 22:48:31 -06:00
tangxifan 9d9840d9b7 [Arch] Add architecture using multi-mode DFFs 2021-04-21 19:49:48 -06:00
tangxifan 16e02ef485 [Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script 2021-04-16 20:47:39 -06:00
tangxifan 4239bb4e68 [Arch] Patch architecture files using multi-mode DFFs 2021-04-16 19:59:55 -06:00
tangxifan f2f7f010ea [Arch] Add new architectures using DFF with reset in VPR 2021-04-16 19:26:18 -06:00
tangxifan 64294ae4eb [Doc] Update README for architecture files due to new architecture features 2021-04-16 19:25:54 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan fdec72b5bc [Arch] Add an example architecture with 8-bit single-mode multiplier 2021-03-23 15:35:06 -06:00
tangxifan 911979a731 [Arch] Update heterogenous architecture for vtr benchmark by adding mult36 2021-03-20 18:04:59 -06:00
tangxifan 910f8471dd [Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys) 2021-03-17 15:10:05 -06:00
tangxifan baf162e401 [Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification 2021-03-10 22:45:19 -07:00
tangxifan 2daa770319 [Arch] Update openfpga architecture to include quicklogic cell sim 2021-03-08 21:40:29 -07:00
tangxifan 4c2a88e27f [Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed 2021-02-24 11:51:10 -07:00
tangxifan 0ce9b66c75 [Arch] Add a dummy adder lut circuit model to support HDL simulation 2021-02-24 10:09:44 -07:00
tangxifan ca135f3325 [Arch] Add flagship architecture with 8-clock 2021-02-22 15:01:18 -07:00
tangxifan 1c09c55e9f [Arch] Add hetergenenous 8-clock FPGA architecture 2021-02-22 13:38:50 -07:00
tangxifan 0ac75723af [Arch] Add new architecture with 8 clocks 2021-02-22 11:00:45 -07:00
tangxifan d85d6e964e
Merge pull request #227 from watcag/master 
Standard-cell flow
 2021-02-17 10:11:34 -07:00
tangxifan b81b74aa7c [Arch] Patch architecture to support superLUT-related XML syntax 2021-02-09 20:23:32 -07:00
tangxifan 304b26c97f [Arch] Add example architectures for superLUT circuit model 2021-02-09 15:11:12 -07:00
Nachiket Kapre 485708423c no need for dff*, but need tap_buf4 2021-02-08 23:00:13 -05:00
Nachiket Kapre 45437fbc46 no need for dff*, but need tap_buf4 2021-02-08 22:27:57 -05:00
Nachiket Kapre 853bf8af43 typos fixed; 2021-02-08 22:03:14 -05:00
Nachiket Kapre 0c6d27cf7e merge for consideration; 2021-02-08 21:26:48 -05:00
tangxifan a6354fab7c [Arch] Decide to move external bitstream definition to a separated XML file 2021-02-01 15:57:44 -07:00
tangxifan df88e2adc0 [Arch] Add an example definition of external bitstream to openfpga arch with soft adder 2021-02-01 14:26:11 -07:00
tangxifan d8927e12e8 [Arch] Add soft adder operating mode to test architecture 2021-02-01 12:25:37 -07:00
tangxifan e4abe263c3 [Arch] Bug fix 2021-02-01 11:29:27 -07:00
tangxifan fb05e1a938 [Arch] bug fix due to using openfpga cell library 2021-02-01 11:27:21 -07:00
tangxifan 0eb949b85a [Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA 2021-02-01 10:34:32 -07:00
tangxifan 6ede799c16 [Arch] Add openfpga architecture for the QLSOFA 2021-02-01 10:15:35 -07:00