tangxifan
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373566416c
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
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cc974a80f7
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[arch] added a new architecture to test the local routing architecture where reset is on LUT
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2022-09-09 16:48:10 -07:00 |
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tangxifan
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95d7a17b3c
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Merge branch 'master' into vtr_upgrade
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2022-09-09 14:32:42 -07:00 |
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tangxifan
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b1fad0b4e5
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[arch] add an example architecture to show the use extended syntax
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2022-09-08 16:19:21 -07:00 |
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tangxifan
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b6e1175517
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[script] update doc and avoid modify README.MD when updating arch files
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2022-08-22 18:19:23 -07:00 |
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tangxifan
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812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
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7598455497
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[Doc] Update naming convention for architecture files
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2022-01-02 19:51:09 -08:00 |
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tangxifan
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81966c2131
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[Doc] Update README for DSP blocks
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2022-01-02 18:27:37 -08:00 |
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tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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16b4e89326
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[Doc] Update documentation for VPR architectures
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2021-01-12 17:57:40 -07:00 |
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tangxifan
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f21d22f691
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[Doc] Update README for new architectures
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2021-01-10 10:54:59 -07:00 |
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tangxifan
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186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
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tangxifan
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eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
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049ca14461
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[Doc] Add new naming rules for vpr architecture files
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2020-11-04 16:17:56 -07:00 |
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tangxifan
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1ca2829868
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update readme for vpr architecture naming
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2020-08-17 13:54:26 -06:00 |
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tangxifan
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1e6955aaa4
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |