tangxifan
|
f081cef495
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add fabric key library
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2020-06-12 00:07:04 -06:00 |
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tangxifan
|
58807bfcb3
|
remove simulation settings from openfpga arch data structure
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
f26550141f
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add missing files
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
15f087598c
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split simulation settings to a separated XML file
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2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
8267dad8ef
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add decoder support for Z signals
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2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a26bb5eef
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add advanced check in configurable memories
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
62c506182c
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start developing frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |
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tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
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2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
|
e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
|
6eb125ec2a
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Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
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2020-04-06 14:09:52 -06:00 |
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tangxifan
|
5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
|
59c13550e0
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add direct annotation with inter-column/row syntax
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2020-02-14 17:40:59 -07:00 |
|
tangxifan
|
df3ae60954
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add default configurable memory model set-up when reading openfpga architecture XML
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2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
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2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
24b180b298
|
change the mode bit storage in annotation data structure from string to vector of integers
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2020-01-29 11:59:20 -07:00 |
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tangxifan
|
7d4b07421d
|
finish XML parser and writer for pb_type annotation
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2020-01-26 15:54:49 -07:00 |
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tangxifan
|
1cba141dd0
|
add pb parser and support XML parsing for pb type name in full hiearchy
|
2020-01-26 11:52:58 -07:00 |
|
tangxifan
|
cd3565cf53
|
complete the XML parser for pb_type annotation
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2020-01-26 10:56:57 -07:00 |
|
tangxifan
|
a9f03ce21b
|
add XML attribute parsing for physical and operating pb_type annotation
|
2020-01-26 10:19:47 -07:00 |
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tangxifan
|
bafd866cfc
|
start developing XML parser for pb_type annotation
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2020-01-25 21:19:08 -07:00 |
|
tangxifan
|
b6f96e5a8f
|
add method functions to pb_type annotation
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2020-01-25 20:46:21 -07:00 |
|
tangxifan
|
9b4b6ae083
|
rename pb_annotation and move it to openfpga namespace
|
2020-01-25 18:17:00 -07:00 |
|
tangxifan
|
f834954698
|
start developing the pb_type annotation
|
2020-01-25 18:14:38 -07:00 |
|
tangxifan
|
b4f4bf62a2
|
add comments to sample arch
|
2020-01-25 17:42:24 -07:00 |
|
tangxifan
|
7feeee8c0e
|
add full syntax to sample_arch.xml about the physical pb_type binding
|
2020-01-25 17:38:06 -07:00 |
|
tangxifan
|
655f84b00e
|
add write_openfpga_arch command to openfpga shell
|
2020-01-23 20:58:15 -07:00 |
|
tangxifan
|
a03f8aa346
|
add profiling for read arch
|
2020-01-23 20:12:30 -07:00 |
|
tangxifan
|
cdb3b6de46
|
add read_openfpga_arch to OpenFPGA shell
|
2020-01-23 19:10:53 -07:00 |
|
tangxifan
|
16752b7e39
|
update on sample arch
|
2020-01-20 12:42:08 -07:00 |
|
tangxifan
|
07994d424c
|
add XML parser and writer for direct connection
|
2020-01-19 15:00:19 -07:00 |
|
tangxifan
|
10336cbe67
|
add XML parser and writer for routing circuit definition for OpenFPGA architecture
|
2020-01-19 14:44:27 -07:00 |
|
tangxifan
|
ebe46d15a9
|
add XML parser, writer and linker for configuration protocol data structure
|
2020-01-18 21:19:20 -07:00 |
|
tangxifan
|
9693c3a12d
|
add XML writer for simulation setting object
|
2020-01-18 16:41:42 -07:00 |
|
tangxifan
|
bc3130d196
|
add XML parser for simulation setting
|
2020-01-18 15:40:20 -07:00 |
|
tangxifan
|
2a902c7e55
|
add mutators to simulation setting data structure
|
2020-01-18 14:07:37 -07:00 |
|
tangxifan
|
0de9908d52
|
add accessors to simulation setting data structure
|
2020-01-18 12:51:25 -07:00 |
|
tangxifan
|
7a46c85cb0
|
reorganize and clean-up sample architecture
|
2020-01-18 10:50:15 -07:00 |
|
tangxifan
|
ab1b1b7e02
|
add XML writer for technology library
|
2020-01-17 20:02:56 -07:00 |
|
tangxifan
|
8f2936af54
|
finish XML parser for technology library
|
2020-01-17 17:43:55 -07:00 |
|
tangxifan
|
e54760c677
|
add XML parsing for transistors and RRAM parameters in technology library
|
2020-01-17 17:32:42 -07:00 |
|
tangxifan
|
d48a888804
|
add XML parsing for design parameters in technology library
|
2020-01-17 17:22:09 -07:00 |
|
tangxifan
|
de0bcc96fb
|
add missing file about XML parsers for technology library
|
2020-01-17 17:16:32 -07:00 |
|
tangxifan
|
d58186507c
|
add XML parsing for device model library settings
|
2020-01-17 17:15:58 -07:00 |
|
tangxifan
|
88a96673e3
|
rename some methods in technology library and start building associated XML parser
|
2020-01-17 16:44:57 -07:00 |