tangxifan
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d391983e8c
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passing regression test on dpram benchmarks
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2019-11-07 14:57:46 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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5cb3717433
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add single mode test case to regression test. debugging now
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2019-10-28 15:57:17 -06:00 |
AurelienUoU
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cc0bfdd548
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Add testcase in regression test for architecture with 1 IO cell/IO block
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2019-09-20 10:27:26 -06:00 |
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tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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tangxifan
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5abbfd6a0f
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add tileable routing to regression test
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2019-09-16 20:45:02 -06:00 |
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tangxifan
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94538b5062
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add more testing architecture
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2019-08-27 18:44:58 -06:00 |
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tangxifan
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3fb3082447
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add more tests
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2019-08-23 14:10:01 -06:00 |
Ganesh Gore
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52d6a9e979
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-23 13:41:29 -06:00 |
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Ganesh Gore
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28dde899db
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Updated Architecture Template
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2019-08-23 12:44:45 -06:00 |
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tangxifan
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520630c5e2
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add more testing tasks
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2019-08-23 10:16:52 -06:00 |
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Ganesh Gore
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5116aa2ae1
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Added architecture and replaced variables
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2019-08-19 19:02:50 -06:00 |
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Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |