tangxifan
|
e863333f22
|
[test] relax route W to bypass VPR bugs
|
2024-11-13 19:01:55 -08:00 |
|
tangxifan
|
b6b75fd19c
|
[test] bypass vtr bugs
|
2024-10-17 14:58:56 -07:00 |
|
tangxifan
|
aa86381d65
|
[test] adjust route chan width to avoid vpr bug on min route chan width (some case failed)
|
2024-10-07 17:17:36 -07:00 |
|
tangxifan
|
33a253da3d
|
[core] fixed the bug
|
2024-09-20 22:20:41 -07:00 |
|
tangxifan
|
6551ca81e5
|
[core] debugging
|
2024-09-20 19:48:02 -07:00 |
|
tangxifan
|
6d3d36626e
|
[test] typo
|
2024-09-20 19:29:47 -07:00 |
|
tangxifan
|
ed33b62a60
|
[test] add new tests to validate intermediate drivers in clock
|
2024-09-20 19:27:40 -07:00 |
|
tangxifan
|
f912af513b
|
[test] add a new testcase to validate mapping gnet to msb during pb_pin_fix
|
2024-09-09 13:54:20 -07:00 |
|
tangxifan
|
2c35840457
|
[test] add a new test to validate CHANY clock spin in DEC
|
2024-08-15 14:24:31 -07:00 |
|
tangxifan
|
586dd1a510
|
[test] add a new and strong test to validate the disable unused clock spines
|
2024-08-15 10:24:58 -07:00 |
|
tangxifan
|
84cc7090ce
|
[test] add a new test to validate that pb pin fixup impacts global net now
|
2024-08-14 10:37:46 -07:00 |
|
tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
|
2024-08-02 18:34:59 -07:00 |
|
tangxifan
|
91c4336a4a
|
[test] add a new testcase to validate 3-layer clock architecture
|
2024-08-02 18:18:49 -07:00 |
|
tangxifan
|
3181f2d5a3
|
[test] add a new test to validate multiple entry points for a clock network
|
2024-07-30 14:17:14 -07:00 |
|
tangxifan
|
f9f9aab7d9
|
[test] typo
|
2024-07-30 12:50:14 -07:00 |
|
tangxifan
|
ad275fba44
|
[test] add a new test to validate clock network entry point on a y-direction cb
|
2024-07-30 12:48:35 -07:00 |
|
tangxifan
|
e614ca7380
|
[test] use new syntax
|
2024-07-10 15:03:27 -07:00 |
|
tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |
|
tangxifan
|
dbe8e63f53
|
[test] remove unused files
|
2024-07-10 10:15:47 -07:00 |
|
tangxifan
|
77304164f4
|
[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
|
2024-07-10 10:13:41 -07:00 |
|
tangxifan
|
191a3d1c5e
|
[test] update W
|
2024-07-10 10:01:31 -07:00 |
|
tangxifan
|
81fe722d98
|
[test] adjust W
|
2024-07-09 23:49:01 -07:00 |
|
tangxifan
|
43dbeafd44
|
[test] typo
|
2024-07-09 20:27:28 -07:00 |
|
tangxifan
|
9ce4b57363
|
[test] typo
|
2024-07-09 20:25:39 -07:00 |
|
tangxifan
|
e5d146a67a
|
[test] add new tests to validate rst on lut and clk on lut features
|
2024-07-09 20:24:23 -07:00 |
|
tangxifan
|
7e461b09f8
|
[core] add missing file
|
2024-07-02 13:22:41 -07:00 |
|
tangxifan
|
e00312d29e
|
[test] typo
|
2024-07-01 20:34:37 -07:00 |
|
tangxifan
|
1bfcf7574c
|
[test] validate region and single syntax
|
2024-07-01 20:33:28 -07:00 |
|
tangxifan
|
28e3cb799e
|
[test] update 2-clock arch and pcf
|
2024-06-29 17:40:20 -07:00 |
|
tangxifan
|
12c9686c27
|
[test] fixed some bugs on arch
|
2024-06-29 17:38:34 -07:00 |
|
tangxifan
|
5dd0549aed
|
[core] typo
|
2024-06-29 17:17:54 -07:00 |
|
tangxifan
|
bc2f02866d
|
[test] update testcase for 2-clk on programmable clock network
|
2024-06-29 17:17:05 -07:00 |
|
tangxifan
|
286df30947
|
[test] update clock arch xml syntax
|
2024-06-29 11:02:17 -07:00 |
|
tangxifan
|
67554cb8d8
|
[test] now use correct pcf for clock network testcases
|
2024-06-29 10:04:03 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
|
2024-06-28 23:06:21 -07:00 |
|
tangxifan
|
1c69365938
|
[core] debugging
|
2024-06-28 18:17:38 -07:00 |
|
tangxifan
|
f1a4304ee7
|
[test] add new testcases for validate clock tree disable functions
|
2024-06-28 13:43:53 -07:00 |
|
tangxifan
|
ad5795bece
|
[test] add extra options to route clock rr_graph command in examples
|
2024-06-28 13:39:41 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
2cbb04b90d
|
[test] add a new testcase to validate programmable clock network with internal drivers
|
2024-06-25 11:58:05 -07:00 |
|
tangxifan
|
9bb076d892
|
[test] fixed a bug on pin mapping of tetbenche
|
2024-06-21 20:29:21 -07:00 |
|
tangxifan
|
8d7dba2d57
|
[test] add a new testcase to programmable clock network on supporting reset signals
|
2024-06-21 18:13:37 -07:00 |
|
tangxifan
|
6c5988575c
|
[test] update clock network testcase
|
2024-06-21 16:59:21 -07:00 |
|
tangxifan
|
fba0a83679
|
[test] debugging 2-clock network
|
2023-04-20 14:44:01 +08:00 |
|
tangxifan
|
02b02d18a5
|
[test] fixed a bug in clock arch
|
2023-04-20 11:35:36 +08:00 |
|
tangxifan
|
b242fd97d6
|
[test] adding new arch and testcase for 2-clock network
|
2023-04-20 11:31:49 +08:00 |
|
tangxifan
|
03cb664049
|
[test] now clock network example script supports multiple clocks
|
2023-04-20 10:56:36 +08:00 |
|
tangxifan
|
7d333b3669
|
[test] add a new test for clock network: validate full testbench is working
|
2023-04-20 10:36:08 +08:00 |