tangxifan
|
ac9046b7d2
|
[Doc] Remove ``define_simulation.v`` since it is no longer needed.
|
2021-06-29 15:38:35 -06:00 |
tangxifan
|
30027b8c15
|
[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
|
2021-06-25 15:27:15 -06:00 |
tangxifan
|
b83d8826fb
|
[Doc] Update documentation on the testbench organization/waveforms
|
2021-06-03 16:54:13 -06:00 |
tangxifan
|
b857135f4e
|
[Doc] Add clarification about which cells are applicable for signal initialization
|
2020-11-23 15:19:15 -07:00 |
tangxifan
|
fd0e6814ea
|
[Doc] Update documentation about the pre-processing flags
|
2020-11-22 20:33:15 -07:00 |
tangxifan
|
56ab63d939
|
[Documentation] Fix format in table
|
2020-10-06 12:02:15 -06:00 |
tangxifan
|
113708c68f
|
[Documentation] Reorganization the overview part by adding technical highlights
|
2020-10-06 11:56:10 -06:00 |
tangxifan
|
67300af987
|
[Documentation] Update motivation with new set of figures
|
2020-09-29 16:52:16 -06:00 |
tangxifan
|
aa77ee9af6
|
add tutorial for full testbench run
|
2020-06-11 19:31:09 -06:00 |
tangxifan
|
dcce782a46
|
update documentation about Verilog testbenches
|
2020-06-11 19:31:08 -06:00 |