tangxifan
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27200e3daa
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[Test] Update regression test cases for fpga verilog
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2021-02-28 12:24:36 -07:00 |
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tangxifan
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ff29cc3dff
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[Test] Move tests to a test group
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2021-02-28 12:23:35 -07:00 |
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tangxifan
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9cb1ca42fe
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[Test] Deploy default net type option to test case
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2021-02-28 12:20:43 -07:00 |
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tangxifan
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ae05871b1f
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[Script] Remove default net type from an example script; Limit it to some test cases
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2021-02-28 12:19:14 -07:00 |
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tangxifan
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d7eb159726
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[Script] Add default net type option to example openfpga shell scripts
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2021-02-28 12:08:30 -07:00 |
Lalit Sharma
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1082d3c677
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Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |
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Lalit Sharma
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1e48d4f6dc
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Modifying custom yosys script file name
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2021-02-25 22:21:39 -08:00 |
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tangxifan
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19f6b221b1
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[Test] Rework comments on runtime
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2021-02-22 15:25:57 -07:00 |
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tangxifan
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4803b0ce42
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[Test] Add test case for sdc controller
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2021-02-22 15:02:14 -07:00 |
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tangxifan
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c7a9a4e896
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[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
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2021-02-22 15:01:50 -07:00 |
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tangxifan
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ca135f3325
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[Arch] Add flagship architecture with 8-clock
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2021-02-22 15:01:18 -07:00 |
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tangxifan
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2e2b1cb6e7
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[Test] Use hetergenenous FPGA architecture in quicklogic tests
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2021-02-22 13:41:04 -07:00 |
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tangxifan
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1c09c55e9f
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[Arch] Add hetergenenous 8-clock FPGA architecture
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2021-02-22 13:38:50 -07:00 |
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tangxifan
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b3fed683f9
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[Test] Deploy test to CI
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2021-02-22 12:43:30 -07:00 |
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tangxifan
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bc30f62c5a
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[Test] Add test for sdc controller
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2021-02-22 12:41:53 -07:00 |
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tangxifan
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60dc194d8f
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[Test] Bug fix in the 5clock test case
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2021-02-22 11:46:23 -07:00 |
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tangxifan
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71e0026a50
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[Test] Add new test for 5-clock counter to quicklogic tests
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2021-02-22 11:32:17 -07:00 |
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tangxifan
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2bb588dacf
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[Flow] Add a new script for generating bitstream for multi-clock architectures
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2021-02-22 11:31:24 -07:00 |
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tangxifan
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77896379e2
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[Arch] Add simulation setting for 8-clock architectures
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2021-02-22 11:10:03 -07:00 |
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tangxifan
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16debe49f6
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[Arch] Add more comments on the 4 clock simulation setting file
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2021-02-22 11:04:34 -07:00 |
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tangxifan
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0ac75723af
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[Arch] Add new architecture with 8 clocks
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2021-02-22 11:00:45 -07:00 |
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tangxifan
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b9c2564a7e
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[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
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2021-02-22 10:49:21 -07:00 |
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tangxifan
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bc8aa0ebc6
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[Test] Remove routing test from quicklogic's flow test
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2021-02-22 10:22:47 -07:00 |
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tangxifan
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2dbdc2644f
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[Benchmark] Remove replicate micro benchmarks
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2021-02-22 10:22:19 -07:00 |
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tangxifan
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9b6b2068ee
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[Test] Move MCNC test to benchmark sweep test group
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2021-02-22 10:18:34 -07:00 |
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tangxifan
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c1f4a434e4
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[Doc] Update README for the regression test tasks
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2021-02-22 10:17:02 -07:00 |
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tangxifan
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d6a02a985e
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Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
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2021-02-22 09:02:29 -07:00 |
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Lalit Sharma
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d842026672
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Disabling verilog testbench generation for quicklogic tests
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2021-02-21 21:58:23 -08:00 |
Lalit Narain Sharma
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be5e0cdea9
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Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
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2021-02-22 09:50:26 +05:30 |
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Lalit Sharma
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576e6753f6
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Removing 2 more tests which are variant of and design
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2021-02-19 09:11:19 -08:00 |
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Lalit Sharma
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d4c5a5655a
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Removing blif file as well as and2 testcase
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2021-02-19 08:55:17 -08:00 |
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Lalit Sharma
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6de0954ca5
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Uncommenting all benchmarks except 2 that requires multiple clocks
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2021-02-19 08:40:26 -08:00 |
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tangxifan
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e08ac1a41e
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[Test] Deploy synthesizable verilog test to CI
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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e19fc15fec
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[Test] bug fix in test case
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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affc8cbbc4
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[Test] Deploy test to CI
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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2e88b035ed
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[Test] Add wire LUT repacker test case
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2021-02-18 19:37:44 -07:00 |
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tangxifan
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1f097abe99
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[Benchmark] Add micro benchmark for FIR filter
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2021-02-18 19:37:44 -07:00 |
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Lalit Sharma
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69cdc11ea5
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Uncommenting the tests that are running fine
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2021-02-18 04:17:12 -08:00 |
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tangxifan
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d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |
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Lalit Sharma
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7ee01711c2
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Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
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2021-02-17 00:06:59 -08:00 |
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Lalit Sharma
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44a979288b
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Adding quicklogic tests and updating the corresponding conf file to run them
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2021-02-16 23:08:38 -08:00 |
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tangxifan
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a819375f69
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[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
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2021-02-16 16:53:13 -07:00 |
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tangxifan
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2c2e493739
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[Test] Remove quicklogic test from basic tests
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2021-02-16 12:29:10 -07:00 |
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tangxifan
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9c19e2b365
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[Test] Move regression test scripts from workflow to openfpga_flow
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2021-02-16 11:55:47 -07:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
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Tarachand Pagarani
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3a587f663a
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copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
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tangxifan
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e683e00032
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[HDL] Add disclaimer for the frac_lut4_arith HDL codes
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2021-02-10 14:50:11 -07:00 |
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tangxifan
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9b86f3bb85
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Merge branch 'master' into dev
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2021-02-09 22:40:45 -07:00 |
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tangxifan
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22e675148e
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[HDL] Add HDL codes for a super LUT with embedded carry logic
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2021-02-09 21:13:22 -07:00 |
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tangxifan
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b81b74aa7c
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[Arch] Patch architecture to support superLUT-related XML syntax
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2021-02-09 20:23:32 -07:00 |