tangxifan
|
4412bbd084
|
[Benchmark] Add a micro benchmark to test pipelined architecture
|
2021-01-10 10:21:30 -07:00 |
tangxifan
|
367cf59efd
|
[Benchmark] Bug fix in the and2_or2 benchmark
|
2020-09-17 10:35:13 -06:00 |
tangxifan
|
de48b8c7b2
|
[Benchmark] Add a new micro benchmark to test fracturable LUTs
|
2020-09-17 10:21:25 -06:00 |
tangxifan
|
f33422d4d7
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
tangxifan
|
cec6bf0b6f
|
add or2 microbenchmark for testing external arch bitstream
|
2020-07-27 15:59:03 -06:00 |
tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
|
2020-07-22 13:17:05 -06:00 |
tangxifan
|
7d39e136a4
|
enrich micro benchmarks
|
2020-07-22 12:33:52 -06:00 |
tangxifan
|
c87dbc4880
|
start using counter benchmark in regression tests
|
2020-06-11 19:31:15 -06:00 |
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
f6cea1e17c
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
3c781b18d3
|
Added routing benchmark
|
2020-06-11 19:31:01 -06:00 |
tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
|
2020-04-20 13:37:39 -06:00 |
tangxifan
|
489ca75230
|
adapt benchmark and_latch module name to be different than benchmark and
|
2020-04-20 13:15:05 -06:00 |
tangxifan
|
8b03ec900f
|
fine-tune micro benchmark to fit port mapping in testbenches
|
2020-04-19 17:05:12 -06:00 |
tangxifan
|
32ed609238
|
update micro benchmark set and regression tests using them
|
2020-04-19 12:49:07 -06:00 |
ganeshgore
|
eb3b02277a
|
Added XML and benchmarks for testing
|
2020-04-06 00:32:06 -06:00 |