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OpenFPGA
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48 Commits

Author SHA1 Message Date
tangxifan 5414a6a3da [Script] Add yosys script with custom DFF tech mapping 2021-04-16 20:00:30 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan 6b0409da60 [Script] Add a template yosys script support only DSP mapping 2021-03-23 15:32:10 -06:00
tangxifan 23e7f7f1f5 [Script] Update default list of result extraction for openfpga flow 2021-03-23 11:06:42 -06:00
tangxifan 7fd345a616 [Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs 2021-03-22 10:39:47 -06:00
tangxifan 1185f7b8bf [Script] Add a template yosys script to enable DSP mapping 2021-03-20 17:05:30 -06:00
tangxifan 7eeb35d21f [Script] Bug fix in yosys script to synthesis BRAM 2021-03-17 15:12:04 -06:00
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan 094b3e9b90 [Script] Use parameters in template yosys script supporting BRAMs 2021-03-16 19:51:48 -06:00
tangxifan 84778bd38d [Script] Add new yosys script to support architectures with BRAMs 2021-03-16 16:52:18 -06:00
tangxifan 76837e02e6 [Script] Rename yosys script supporting bram and restructure techlib files 2021-03-16 16:16:53 -06:00
tangxifan 90a00da1df [Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset' 2021-03-10 13:56:35 -07:00
tangxifan 0e772bc3b4 [Script] Patch the yosys rewrite script to avoid existing blif outputs 2021-03-10 13:47:30 -07:00
tangxifan 7adb78b159 [Script] Add a template yosys script with rewriting at the end 2021-03-10 13:40:31 -07:00
tangxifan 812d8c950e [Script] Update quicklogic's script to output correct verilog file name 2021-03-08 21:39:44 -07:00
tangxifan c53c41b7a5 [Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file 2021-03-08 21:09:23 -07:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Lalit Sharma 2b2acae757 Adding command to generate verilog file out of yosys run 2021-03-05 04:07:02 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
Lalit Sharma 0038496d9c Replacing -openfpga with -family qlf_k4n8 2021-02-28 21:08:47 -08:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
Ganesh Gore df4a397470 [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00
Lalit Sharma ebe66dea35 Bumping up latest yosys changes related to adder tech mapping 2021-02-03 14:30:06 +05:30
Lalit Sharma 8a5741b1ae Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow 2021-01-08 07:08:24 -08:00
Lalit Sharma 3c9e4919b4 Updating variable name in ys to call BLIF output file. 2020-12-18 03:18:46 -08:00
Lalit Sharma 1f994319fd Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF 2020-12-16 04:19:56 -08:00
Lalit Sharma 891e2f8aa3 Adding arch xml from SOFA repo. Also updating the script with its file location 2020-12-16 04:14:18 -08:00
Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow 2020-12-10 02:41:43 -08:00
Andrew Lukefahr 2d92a1f1af Edits to enable basic run_fpga_flow.py 2020-10-02 10:18:10 -04:00
ganeshgore 890ead91b9 Fixed modelsim include references 2020-06-11 19:28:13 -06:00
ganeshgore ea4122a8a4 Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
AurelienUoU 09fd2afa9c Adding heterogeneous synthesis requirements 2019-12-03 16:09:26 -07:00
Ganesh Gore f05aede868 Added task support for modelsim script 2019-11-15 23:23:15 -07:00
Ganesh Gore 27005d6640 Added Modelsim Python Script 2019-11-01 18:20:40 -06:00
Ganesh Gore d269472daf Updated formality python script 2019-09-27 14:00:57 -06:00
Ganesh Gore d64bb18346 Separated Modelsim tcl script generation 2019-09-07 12:36:22 -04:00
Ganesh Gore f558437ae1 Added task for vpr_blif flow 2019-08-25 00:23:39 -06:00
Ganesh Gore 30cbe38d3d Added Test Modes - Added blif VPR Option 2019-08-22 17:00:59 -06:00
Ganesh Gore afee2229af Removed unused templates and file from openfpga_flow directory 2019-08-19 21:32:52 -06:00
Ganesh Gore 08b0ef3550 Updated validate_command_line_arguments function 
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
 2019-08-19 21:28:23 -06:00
Ganesh Gore 616d7706c9 Added list of intermidiate files filename 2019-08-19 19:05:08 -06:00
Ganesh Gore 8f8707ff98 Added option to filter results after parsing 2019-08-19 19:04:14 -06:00
Ganesh Gore cb5b16c949 Moved required files to openfpga folder 2019-08-19 18:57:42 -06:00
Ganesh Gore 5d3708651e Added fpga_flow and fpga_task script 
+ Missed local intermediate commits
 2019-08-15 14:39:58 -06:00
Ganesh Gore 9ab57d1b2e Added fpga_flow script - Working Yosys 2019-08-09 16:49:05 -06:00
Ganesh Gore b82369dd96 Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00