tangxifan
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21a18069a1
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[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
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2021-05-24 14:50:55 -06:00 |
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tangxifan
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b6b98a75b8
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[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
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2021-05-24 13:03:40 -06:00 |
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tangxifan
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1c4dc9f74b
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[Doc] Update documentation about the super LUT feature
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2021-02-10 11:49:59 -07:00 |
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tangxifan
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9c5368f912
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[Doc] Correct bugs in compiling latexpdf
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2021-02-07 16:17:54 -07:00 |
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tangxifan
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226f6b8d6d
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
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tangxifan
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406edeec89
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[Doc] Typo fix
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2020-12-04 15:07:02 -07:00 |
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tangxifan
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4fe190fa7e
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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tangxifan
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cc0114459a
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[Doc] Enrich examples for LUT circuit models
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2020-11-26 13:03:12 -07:00 |
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tangxifan
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2b9a97729e
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[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
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2020-11-23 15:09:47 -07:00 |
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tangxifan
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056b7c0c79
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[Doc] Update documentation about CCFF circuit model examples
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2020-11-06 12:22:22 -07:00 |
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tangxifan
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ccaa697e5a
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[Documentation] Add links to technical features to examples
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2020-10-10 22:40:37 -06:00 |
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tangxifan
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de07712a3a
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update documentation about the frame-based configuration protocol
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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c27d77a418
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clean-up documentation for a shallow hierarchy
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2020-06-11 19:31:08 -06:00 |