tangxifan
|
812553e13d
|
[test] adding more test cases
|
2023-05-25 20:17:23 -07:00 |
|
tangxifan
|
df771cb33a
|
[test] add a new testcase for subtile and deploy it to basic regression test
|
2023-05-03 15:41:29 +08:00 |
|
tangxifan
|
f06248a1b0
|
[test] add a new testcase to validate the ccff v2
|
2023-04-24 14:55:22 +08:00 |
|
tangxifan
|
02e964b16f
|
[test] add a new test case for ccffv2
|
2023-04-22 15:41:19 +08:00 |
|
tangxifan
|
087636cefa
|
[test] deploy new test to regression tests
|
2023-04-20 15:06:47 +08:00 |
|
tangxifan
|
7d333b3669
|
[test] add a new test for clock network: validate full testbench is working
|
2023-04-20 10:36:08 +08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
Ganesh Gore
|
4f6b8c0905
|
Updated regression tests
|
2023-02-11 22:11:06 -07:00 |
|
tangxifan
|
8174f53796
|
[test] deploy new test to fpga bitstream regression
|
2023-01-24 15:42:01 -08:00 |
|
tangxifan
|
95dd4fd535
|
[test] deploy new test to basic regression tests
|
2023-01-18 18:17:53 -08:00 |
|
tangxifan
|
5aa85d82e6
|
[test] deploy the new test to basic regression tests
|
2023-01-13 22:07:45 -08:00 |
|
tangxifan
|
bbf83101be
|
[test] deploy new test to ci
|
2023-01-11 17:11:28 -08:00 |
|
tangxifan
|
43cb498827
|
[test] deploy new tests to basic regression tests
|
2023-01-01 17:07:25 -08:00 |
|
tangxifan
|
93b020b0b3
|
[test] deploy new test to basic regression tests
|
2022-12-30 18:26:22 -08:00 |
|
tangxifan
|
c33b9f1b9b
|
[script] enable eval mode in tcl reg test
|
2022-12-02 12:07:27 -08:00 |
|
tangxifan
|
156fac9fec
|
[ci] deploy tcl test to ci
|
2022-12-02 11:46:14 -08:00 |
|
tangxifan
|
97c72c73f1
|
[test] add a small test to validate tcl integration
|
2022-12-02 11:43:46 -08:00 |
|
tangxifan
|
609e096b1a
|
[test] added a new test to validate explicit port direction in pin table support
|
2022-10-17 15:25:19 -07:00 |
|
tangxifan
|
aa78981e37
|
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
|
2022-10-17 11:18:21 -07:00 |
|
tangxifan
|
5cf315958d
|
[test] deploy new test to basic regression tests
|
2022-10-13 11:17:34 -07:00 |
|
tangxifan
|
13c819bb28
|
[ci] deply new test to ci
|
2022-10-01 11:04:08 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
e0f632cc9c
|
[test] fixed a bug
|
2022-09-20 20:29:34 -07:00 |
|
tangxifan
|
645d8df7b9
|
[test] fixed a bug
|
2022-09-20 20:09:41 -07:00 |
|
tangxifan
|
9042fc2422
|
[test] now reg test should show diff details when failed
|
2022-09-20 19:32:34 -07:00 |
|
tangxifan
|
da157ed5de
|
[test] debugging git-diff
|
2022-09-20 15:31:39 -07:00 |
|
tangxifan
|
6a896a9845
|
[test] debugging
|
2022-09-20 14:08:22 -07:00 |
|
tangxifan
|
ecfdc4a83a
|
[test] debugging
|
2022-09-20 13:51:32 -07:00 |
|
tangxifan
|
bdcdc7d294
|
[test] Now git diff in basic regression tests should capture the changes on golden outputs
|
2022-09-20 13:36:31 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
a2e22787c2
|
[test] deploy the new test cases to the basic regression tests
|
2022-09-16 10:31:15 -07:00 |
|
tangxifan
|
91fe27ff66
|
[test] deploy new test to ci
|
2022-09-09 17:00:28 -07:00 |
|
tangxifan
|
95d7a17b3c
|
Merge branch 'master' into vtr_upgrade
|
2022-09-09 14:32:42 -07:00 |
|
tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
|
2022-09-06 14:59:00 -07:00 |
|
tangxifan
|
9e1abf5898
|
Merge branch 'master' into vtr_upgrade
|
2022-09-01 21:39:14 -07:00 |
|
tangxifan
|
c48f750f86
|
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
|
2022-09-01 20:10:29 -07:00 |
|
tangxifan
|
71ad0721a1
|
Merge branch 'master' into vtr_upgrade
|
2022-08-31 13:56:17 -07:00 |
|
tangxifan
|
201bca8968
|
[test] typo
|
2022-08-30 08:59:20 -07:00 |
|
tangxifan
|
5f88b9a226
|
[test] typo
|
2022-08-29 22:41:15 -07:00 |
|
tangxifan
|
0b5bdcdbb1
|
[test] deploy new test to basic regression tests
|
2022-08-29 22:07:56 -07:00 |
|
tangxifan
|
8d6682c28b
|
[test] fixed a bug when removing previous runs
|
2022-08-25 16:20:18 -07:00 |
|
tangxifan
|
6ce1d4804c
|
[test] deploy new test case to basic regression tests
|
2022-08-01 21:05:05 -07:00 |
taoli4rs
|
347a29f27c
|
Fix test name in basic regression test script.
|
2022-07-20 21:05:31 -07:00 |
|
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
|
tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
|
tangxifan
|
86347a9d49
|
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |
|
tangxifan
|
7d694acf32
|
[test] debugging basic reg test paths
|
2022-05-23 11:21:36 +08:00 |