Commit Graph

1687 Commits

Author SHA1 Message Date
tangxifan 4d9aacdf8f [test] add and deploy new benchmark 2024-06-02 14:27:02 -07:00
tangxifan ad2d101554 [test] deploy new benchmarks 2024-06-02 14:23:08 -07:00
tangxifan 8f2974d7a1 [test] update golden copies 2024-05-29 10:31:19 -07:00
tangxifan 3c49af6a08 [test] code format 2024-05-20 21:28:46 -07:00
tangxifan f25081eb31 [test] add a new test to validate ecb when tile modules are used 2024-05-20 21:10:49 -07:00
tangxifan 852b01aaff [test] rework 2024-05-20 17:20:04 -07:00
tangxifan a9a5fbee34 [test] add fully connected feedback connections to directlist 2024-05-20 17:02:20 -07:00
tangxifan 807c37d3ff [test] fixed some bugs 2024-05-20 13:47:22 -07:00
tangxifan 6146d0be9f [arch] Move clb I to right side as left side is not supported yet 2024-05-20 13:43:04 -07:00
tangxifan 65dd342c60 [arch] typo 2024-05-20 12:11:22 -07:00
tangxifan 653521755b [test] add new testcase for ecb to basic regtest 2024-05-20 12:09:12 -07:00
tangxifan bdc13e491e [arch] adding openfpga arch for ecb 2024-05-20 12:04:52 -07:00
tangxifan c795dd2f1a [arch] adding a new arch where feedback loops are modelled by direct connections 2024-05-20 12:00:39 -07:00
tangxifan 65a8db4f38 [arch] replace out-of-date keywords 2024-05-20 11:18:46 -07:00
tangxifan 372e386330 [test] add new tests to verify rr graph preloading in two file formats 2024-05-09 23:10:45 -07:00
tangxifan b8b8fb6d3b [test] update golden files 2024-05-07 13:25:23 -07:00
tangxifan 81730da7b2 [test] update golden files 2024-05-07 13:25:04 -07:00
tangxifan e72d71fe28 [test] update golden outputs 2024-05-07 13:24:45 -07:00
tangxifan deee75f828 [test] use a different W to avoid vvp collapse 2024-05-07 12:20:58 -07:00
tangxifan 7a0cd764d3 [test] fixed some bugs 2024-05-07 11:23:33 -07:00
tangxifan 13f8dd096e [test] create a new example script for fixed routing W case 2024-05-07 10:24:15 -07:00
tangxifan 00f39d55ab [test] now use fixed routing channel width 2024-05-06 23:32:27 -07:00
tangxifan 3615bdceeb [test] avoid no-fanin errors for hetero arch 2024-05-06 15:32:27 -07:00
tangxifan 10470b311d [test] now use latest python3 of ubuntu 22.04 2024-05-06 11:44:45 -07:00
tangxifan c334a0a792 [test] fixed a bug and add golden outputs 2024-05-02 22:07:22 -07:00
tangxifan 98006608c2 [test] add fabric hierarchy file to golden outputs 2024-05-02 22:03:23 -07:00
tangxifan 4e3bbbe45e [test] add options to write fabric hierarchy file 2024-05-02 22:00:47 -07:00
chungshien dd577e37e0
LUTRAM Support (#1595)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric

* LUTRAM Support Phase 1

* Add Test

* Add more protocol checking to enable LUTRAM feature

* Move the config setting under config protocol

* Revert any changes

---------

Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
tangxifan 1af8a4ae4f [test] add golden outputs 2024-04-11 15:20:34 -07:00
tangxifan 9b0a491819 [test] now validate no time stamp file for fabric pin physical location 2024-04-11 15:16:34 -07:00
tangxifan d51832a4e2 [ci] typo 2024-04-11 15:13:20 -07:00
tangxifan e85df6dcfd [ci] deploy new tests to basic reg tests 2024-04-11 15:11:41 -07:00
tangxifan 20ba0e1dd5 [test] add new testcases to validate options of write_fabric_pin_physical_location 2024-04-11 15:06:50 -07:00
tangxifan 0c680ec426 [test] now test regex as module name for fabric pin physical location 2024-04-11 15:01:19 -07:00
tangxifan 4dedee4011 [test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command 2024-04-11 12:59:13 -07:00
tangxifan c63cee458b [script] adapt code format for python 2024-04-10 12:58:05 -07:00
tangxifan 3824b006cc [test] add new golden outputs 2024-03-29 12:06:00 -07:00
tangxifan f0639b4567 [test] add new testcase to basic reg test 2024-03-29 11:56:11 -07:00
tangxifan 20386945bd [test] add a new testcase to validate dump waveform 2024-03-29 11:53:55 -07:00
chungshien 4365d160ff
Support extracting data that is not affecting fabric bitstream (#1566)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
tangxifan 2bd60dad11 [script] now timing extraction focus on the last found results 2023-12-12 14:10:13 -08:00
tangxifan 592e2e310c [script] typo 2023-12-12 13:45:23 -08:00
tangxifan b182b47d0b [test] use a timing-focus tool path for a testcase 2023-12-12 13:28:35 -08:00
tangxifan c5cc05a9f5 [script] add a new example default tool path config with a focus on timing 2023-12-12 13:22:50 -08:00
tangxifan f689ef7654 [script] format 2023-12-12 13:15:03 -08:00
tangxifan 4c0f6e2273 [script] syntax 2023-12-12 13:14:47 -08:00
tangxifan e753e6d22c [script] syntax 2023-12-12 13:13:51 -08:00
tangxifan d9db78ac30 [script] now run fpga task has a new option ``default_tool_path`` 2023-12-12 13:11:48 -08:00
tangxifan 1a4aaaf759 [script] update openfpga flow to support args for default tool path 2023-12-12 10:00:50 -08:00
tangxifan a7b22163a8 [script] fixe the mismatch on keywords against latest vpr 2023-12-12 09:52:42 -08:00