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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3 Commits
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tangxifan
5ece7ab6d0
start refactoring the bitstream part using spice_models
2019-08-16 15:58:14 -06:00
tangxifan
eef1312325
updated bitstream to use new RRSwitchBlock as well as the report timing engine
2019-05-24 12:54:10 -06:00
tangxifan
46d44fa42a
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00