Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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Ganesh Gore
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125d7888df
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Merge remote-tracking branch 'origin/spice_model_refactoring' into ganesh_dev
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2019-08-16 22:00:41 -06:00 |
tangxifan
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aa7f3bef7f
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fixed bugs in configure pb_rr_graph and dependence on testbenches
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2019-08-16 18:20:30 -06:00 |
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tangxifan
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e456b6f905
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replace spice_models with circuit model in bitstream generator
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2019-08-16 16:36:49 -06:00 |
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tangxifan
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5ece7ab6d0
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start refactoring the bitstream part using spice_models
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2019-08-16 15:58:14 -06:00 |
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tangxifan
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b66e120366
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patch on local encoders for unused configuration, avoid chip-burn issues
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2019-08-16 15:32:23 -06:00 |
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Ganesh Gore
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4865335627
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Merge remote-tracking branch 'origin/dev' into ganesh_dev
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2019-08-16 14:14:16 -06:00 |
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Ganesh Gore
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c43c3cdf25
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Added VPR output parse option
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2019-08-16 13:36:39 -06:00 |
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Ganesh Gore
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effbd332aa
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Added task report generation
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2019-08-16 10:59:44 -06:00 |
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Ganesh Gore
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901932a4fc
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First draft: Working openfpga task flow
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2019-08-16 09:44:50 -06:00 |
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tangxifan
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4eb046760b
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still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
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2019-08-15 21:57:59 -06:00 |
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Ganesh Gore
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5d3708651e
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Added fpga_flow and fpga_task script
+ Missed local intermediate commits
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2019-08-15 14:39:58 -06:00 |
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tangxifan
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35ad4a87e5
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add travis slack notification
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2019-08-14 12:51:17 -06:00 |
AurelienUoU
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8e38aa6019
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Merge with heterogeneous for unfracturable LUT bug fix
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2019-08-14 10:10:27 -06:00 |
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AurelienUoU
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df873903f8
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Bug fix for non fracturable LUT
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2019-08-14 09:32:15 -06:00 |
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AurelienUoU
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30c0f2b6b7
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-08-14 09:11:54 -06:00 |
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AurelienUoU
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90aaed6e1f
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Fix regression test
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2019-08-14 09:10:13 -06:00 |
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tangxifan
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d2d8af5416
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bug fixing for pb_type num_conf_bits and num_iopads stats
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2019-08-13 17:34:09 -06:00 |
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tangxifan
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edfa72a666
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try to fix the bug in clock net identification
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2019-08-13 16:47:28 -06:00 |
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tangxifan
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1118b28397
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use single subckt for switch box again, to abolish the multi-module subckt
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2019-08-13 16:11:04 -06:00 |
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tangxifan
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4cffd8ac2d
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keep route file updated with tileable rr_graph
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2019-08-13 15:37:42 -06:00 |
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tangxifan
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c7526cb43c
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memory sanitized
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2019-08-13 14:19:40 -06:00 |
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tangxifan
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ef4d15df4e
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reorganize the libarchfpga repository
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2019-08-13 13:37:35 -06:00 |
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tangxifan
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392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
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2019-08-13 13:25:23 -06:00 |
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AurelienUoU
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8dab4dec90
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-08-13 11:09:29 -06:00 |
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AurelienUoU
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7851246424
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Resolve merge issue
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2019-08-13 11:08:30 -06:00 |
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tangxifan
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c56f289d3e
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add checkers for circuit library
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2019-08-12 16:45:33 -06:00 |
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tangxifan
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d4ae160d3a
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start adding circuit library checkers
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2019-08-12 14:20:11 -06:00 |
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AurelienUoU
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2da4d3f33c
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-08-12 09:57:02 -06:00 |
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tangxifan
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fbdab32a2d
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timing graph for circuit models are working
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2019-08-10 13:03:24 -06:00 |
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tangxifan
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c004699a14
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complete parsers for ports
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2019-08-09 21:00:41 -06:00 |
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tangxifan
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2c7d6e3de4
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adding port parsers
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2019-08-09 17:48:55 -06:00 |
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Ganesh Gore
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9ab57d1b2e
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |
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tangxifan
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f80e58c753
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developing a in-house tokenizer
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2019-08-09 16:36:22 -06:00 |
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tangxifan
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3d7adb3dd9
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start developing parsers for delay values
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2019-08-09 15:52:28 -06:00 |
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tangxifan
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6b5ac2e1ef
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add timing graph builder for circuit models
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2019-08-09 12:45:03 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |
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tangxifan
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c8d04c4f00
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plug in fast look-up builder
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2019-08-08 21:20:28 -06:00 |
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Ganesh Gore
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0cc439f76c
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Working lattice benchmark unclean commit
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2019-08-08 18:08:39 -06:00 |
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tangxifan
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158c67075e
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built a conversion from spice_models to circuit_library and plug in
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2019-08-08 17:25:27 -06:00 |
Baudouin Chauviere
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0b46adb5ef
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-08-08 15:17:43 -06:00 |
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tangxifan
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e19485bbb7
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add more accessors and more to be added when plug into framework
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2019-08-08 14:16:29 -06:00 |
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tangxifan
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ad8c33e1ba
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complete the mutators
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2019-08-08 11:33:11 -06:00 |
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tangxifan
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5b0c9572c3
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add mutators for delay_info
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2019-08-07 21:19:16 -06:00 |
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tangxifan
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03a64e2ad8
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complete the mutators for ports
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2019-08-07 20:54:27 -06:00 |
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tangxifan
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9f8c7a3fc7
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adding port mutators
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2019-08-07 17:47:39 -06:00 |
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tangxifan
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ed4642a23f
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adding basic mutators
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2019-08-07 17:12:05 -06:00 |
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tangxifan
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38962c4607
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adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
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tangxifan
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74da4ed51a
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start creating the class for circuit models
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2019-08-07 11:38:45 -06:00 |
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tangxifan
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f57495feba
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Now we can also auto-generate the Verilog for a mux2 std cell
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2019-08-06 15:19:01 -06:00 |