Baudouin Chauviere
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6441f2ebe7
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-10 14:16:55 -06:00 |
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Baudouin Chauviere
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0a978db866
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Fix regression test
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2019-07-10 14:16:34 -06:00 |
tangxifan
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c6a4d29ed8
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Merge branch 'tileable_routing' into dev
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2019-07-10 12:05:43 -06:00 |
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tangxifan
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57ae5dbbec
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bug fixing for rectangle FPGA sizes
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2019-07-09 20:47:52 -06:00 |
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Baudouin Chauviere
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792ba23f4f
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Correction pre-merge
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2019-07-09 14:34:34 -06:00 |
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Baudouin Chauviere
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589f58b55e
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Regression test succeeded
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2019-07-09 09:18:06 -06:00 |
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Baudouin Chauviere
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25f5bc7792
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Latest version, not stable yet but close
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2019-07-09 08:34:01 -06:00 |
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Baudouin Chauviere
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df0a3d23a3
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Correction top module
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2019-07-08 10:23:14 -06:00 |
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Baudouin Chauviere
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ae05c553d5
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Top module done
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2019-07-08 09:48:33 -06:00 |
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Baudouin Chauviere
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b08513d902
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Big chunk added on the routing part of the explicit mapping
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2019-07-02 14:12:42 -06:00 |
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Baudouin Chauviere
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8f5ad2eb67
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Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
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tangxifan
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5b25bbb120
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bug fixed for direct connection in CBs and direct connection in top netlist
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2019-07-01 17:25:00 -06:00 |
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Baudouin Chauviere
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f189ef1d8f
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Done with the submodules
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2019-07-01 14:24:09 -06:00 |
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Baudouin Chauviere
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370ce23646
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Mux explicit verilog done
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2019-07-01 13:58:24 -06:00 |
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Baudouin Chauviere
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863e8677c0
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Further add new functions to tree
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2019-07-01 12:12:36 -06:00 |
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Baudouin Chauviere
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0e04b88c8f
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Include new files in the parameter spreading
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2019-07-01 11:27:48 -06:00 |
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Baudouin Chauviere
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04eb6d3488
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Correction pre-merge
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2019-06-27 14:33:06 -06:00 |
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Baudouin Chauviere
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7c742f1cbb
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Stable, is_explicit propagated through the code. Not implemented though except for muxes
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2019-06-27 10:29:57 -06:00 |
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tangxifan
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8edd85c9fc
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keep fixing bugs in verilog SDC generator for tileable CBs
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2019-06-26 22:58:52 -06:00 |
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tangxifan
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711e369fe7
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fixing bugs in the SDC generator and report_timing
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2019-06-26 18:09:09 -06:00 |
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tangxifan
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0fe54d87d5
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fixed a bug in SDC generator for constraining SBs in tileable arch
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2019-06-26 17:06:14 -06:00 |
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Baudouin Chauviere
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0ce9846e47
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Stable, unfinished
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2019-06-26 16:54:41 -06:00 |
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tangxifan
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7d85eb544d
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start fixing bugs for SDC generator when using tileable arch
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2019-06-26 16:48:17 -06:00 |
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tangxifan
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f5920c7422
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fix bugs in ptc_num using for SB
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2019-06-26 16:21:02 -06:00 |
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tangxifan
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3d8200e217
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critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
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d2ed82d14d
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 15:00:39 -06:00 |
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tangxifan
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57616361c2
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fixed critical bugs in cb configuration port indices
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2019-06-26 14:58:52 -06:00 |
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Baudouin Chauviere
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d2bd2be76b
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Warnings correction in the make sequence
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2019-06-26 14:33:12 -06:00 |
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Baudouin Chauviere
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87ddca9f57
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commiting current work. Stable but function not implemented yet
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2019-06-26 14:22:02 -06:00 |
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tangxifan
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42f85004b6
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fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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tangxifan
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9b6a4b39bb
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 11:36:08 -06:00 |
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tangxifan
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c879e7f6c5
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
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Baudouin Chauviere
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b7c2954b91
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-26 10:51:55 -06:00 |
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Baudouin Chauviere
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8f21a3b177
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Memory leakage correction
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2019-06-26 10:50:38 -06:00 |
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tangxifan
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d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
AurelienUoU
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ec504049ef
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Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
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Baudouin Chauviere
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56557b94e7
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Bug Fix
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2019-06-26 08:53:46 -06:00 |
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Baudouin Chauviere
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bb250ddef9
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Bug fix in cpp
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2019-06-25 16:47:10 -06:00 |
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Baudouin Chauviere
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332ce17f03
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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Baudouin Chauviere
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be25b6dd66
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-20 14:11:03 -06:00 |
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Baudouin Chauviere
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3bd6c40a10
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Report timing modified to have only one liners
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2019-06-20 14:10:39 -06:00 |
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AurelienUoU
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a7502bb43b
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Avoid configuration bits for module wihch don't require them
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2019-06-20 09:40:41 -06:00 |
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Baudouin Chauviere
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57a4ad1f99
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Break memories even in the clb sdc
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2019-06-16 14:27:29 -06:00 |
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tangxifan
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4d2a3680be
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support bus explicit port mapping to standard cells (for BRAMs)
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2019-06-14 11:09:15 -06:00 |
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tangxifan
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0902d1e75a
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c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
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tangxifan
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af1628abfe
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use bus port for primitives in Verilog generator
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2019-06-13 16:26:58 -06:00 |
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tangxifan
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dddbbac85c
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merge from multimode_clb bug fixing
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2019-06-13 15:59:34 -06:00 |
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tangxifan
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43128ad3f0
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fix a bug in formal verification port for memory bank configuration circuits
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2019-06-13 15:33:13 -06:00 |
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tangxifan
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44d21ebb90
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fixed a bug in Verilog generator supporting SRAM5T
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2019-06-13 14:42:39 -06:00 |
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tangxifan
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1776ae3ec8
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |