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riscv
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OpenFPGA
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tangxifan
6dd8d347e1
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
2020-06-11 19:31:01 -06:00
tangxifan
726185cd5e
add test cases using spypad architecture
2020-04-22 12:56:57 -06:00