4 Commits

Author	SHA1	Message	Date
tangxifan	c87dbc4880	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
tangxifan	9761d13eef	update microbenchmark and2 module name	2020-04-20 13:37:39 -06:00
tangxifan	32ed609238	update micro benchmark set and regression tests using them	2020-04-19 12:49:07 -06:00
tangxifan	59ea0a6ad5	add implicit verilog test case to Travis CI	2020-04-12 20:00:20 -06:00