4 Commits

Author	SHA1	Message	Date
tangxifan	96b58dfdbb	use new simulation setting command in openfpga shell	2020-06-11 19:31:15 -06:00
tangxifan	bba476fef4	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
tangxifan	1943929353	add write_fabric_hierarchy to regression tests	2020-06-11 19:31:04 -06:00
tangxifan	42cede37fa	add testcases on generate fabric/testbench only	2020-06-11 19:31:01 -06:00