tangxifan
|
6645b70ae3
|
[Engine] Upgrade parser to support BL/WL protocols
|
2021-09-23 14:25:25 -07:00 |
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tangxifan
|
d4e3445153
|
[Engine] update internal data structure for new syntax in configuration protocol
|
2021-09-22 17:32:45 -07:00 |
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tangxifan
|
e09ab2298e
|
[Engine] Bug fix in fabric key parser on identifying invalid coordinate
|
2021-09-21 16:45:14 -07:00 |
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tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
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tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
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tangxifan
|
5759f5f35b
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[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
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2021-09-03 17:55:23 -07:00 |
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tangxifan
|
9074bffa68
|
[Tool] Support customized default value in pin constraint file
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2021-07-01 23:43:19 -06:00 |
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tangxifan
|
fed975c52a
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[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
|
tangxifan
|
db9bb9124e
|
[Tool] Add report bitstream distribution command to openfpga shell
|
2021-05-07 11:41:25 -06:00 |
|
tangxifan
|
01b3a96e4b
|
[Tool] Add report bitstream distribution functionality to architecture bitstream library
|
2021-05-07 11:22:01 -06:00 |
|
tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
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tangxifan
|
96ce6b545f
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[Tool] Patch repack to consider design constraints for pins that are not equivalent
|
2021-04-21 13:53:08 -06:00 |
|
tangxifan
|
5364b94cf8
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[Tool] Update bitstream setting parser/writer to support interconnect-related syntax
|
2021-04-19 13:42:12 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
d877a02534
|
[Tool] Patch the extended bitstream setting support on mode-select bits
|
2021-03-10 21:28:09 -07:00 |
|
tangxifan
|
85640a7403
|
[Tool] Extend bitstream setting to support mode bits overload from eblif file
|
2021-03-10 20:45:48 -07:00 |
|
tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
|
2021-03-01 08:38:58 -07:00 |
|
tangxifan
|
73461971d2
|
[Tool] Bug fix for printing single-bit ports in Verilog netlists
|
2021-02-28 16:12:57 -07:00 |
|
tangxifan
|
7a5dd1bc02
|
[Tools] Patch circuit library for dummy circuit models without any ports
|
2021-02-24 10:36:48 -07:00 |
|
tangxifan
|
b2984b46ee
|
[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
|
2021-02-09 21:15:57 -07:00 |
|
tangxifan
|
faabdab815
|
[Tool] Remove redundant tab in bitstream setting writer
|
2021-02-01 18:04:21 -07:00 |
|
tangxifan
|
d5b1cc5ec7
|
[Tool] Bug fix in parser for bitstream settings
|
2021-02-01 18:01:42 -07:00 |
|
tangxifan
|
f102e84497
|
[Tool] Add bitstream setting file to openfpga library
|
2021-02-01 17:43:46 -07:00 |
|
tangxifan
|
3b7762ef85
|
[Lib] Now try to call undefined command will cause a error code to return
|
2021-01-24 17:44:51 -07:00 |
|
tangxifan
|
a8158322ef
|
[Tool] Bug fix in setting command execution status in OpenFPGA shell
|
2021-01-24 17:25:03 -07:00 |
|
tangxifan
|
fd0e73a9bb
|
[Tool] Enhance return code for openfpga shell
|
2021-01-24 14:48:27 -07:00 |
|
tangxifan
|
8cac3291cb
|
[Tool] Add batch mode to openfpga shell execution
|
2021-01-24 14:33:58 -07:00 |
|
tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
ecd955124b
|
[Lib] Add libpcf to CMakelist and bug fix
|
2021-01-19 15:51:14 -07:00 |
|
tangxifan
|
52ac7826eb
|
[Lib] Add a library of parser/writer for pin constraint file (PCF)
|
2021-01-19 15:45:45 -07:00 |
|
tangxifan
|
ea9d6bfe91
|
[Flow] Update the design constraint file to follow bug fix in parser
|
2021-01-17 10:41:01 -07:00 |
|
tangxifan
|
113119bd8e
|
[Lib] Fix the bug in repack design constraint parser
|
2021-01-17 10:39:55 -07:00 |
|
tangxifan
|
2efe513122
|
[Tool] Now repack consider design constraints; test pending
|
2021-01-16 21:57:17 -07:00 |
|
tangxifan
|
d0e05b3575
|
[Lib] Now use pb_type in design constraints instead of physical tiles
|
2021-01-16 21:35:43 -07:00 |
|
tangxifan
|
b86adabe69
|
[Lib] Remove unused data storage from repack design constraints
|
2021-01-16 21:14:52 -07:00 |
|
tangxifan
|
706e84bb62
|
[Lib] Bug fix in testing program
|
2021-01-16 18:15:56 -07:00 |
|
tangxifan
|
67c54c4d3b
|
[Lib] Bug fix in the repack design constraint lib
|
2021-01-16 17:34:22 -07:00 |
|
tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
|
2021-01-16 17:20:59 -07:00 |
|
tangxifan
|
9d80f1ab39
|
[Lib] Add test program to the library of repack design constraints
|
2021-01-16 17:18:42 -07:00 |
|
tangxifan
|
03b5bcc244
|
[Lib] Add XML writer for repack design constraints
|
2021-01-16 17:15:31 -07:00 |
|
tangxifan
|
2a7601fb7e
|
[Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints
|
2021-01-16 17:14:51 -07:00 |
|
tangxifan
|
f1bfa2ef8c
|
[Lib] Add XML parser for repack design constraints
|
2021-01-16 17:03:01 -07:00 |
|
tangxifan
|
8be12b6e82
|
[Lib] Add example design constraint file
|
2021-01-16 16:36:10 -07:00 |
|
tangxifan
|
a926c74ae5
|
[Lib] Add CMake script to compile the repack design constraint library
|
2021-01-16 16:35:46 -07:00 |
|
tangxifan
|
b57dc7b898
|
[Lib] Add repack design constraint library
|
2021-01-16 16:35:13 -07:00 |
|
tangxifan
|
b8e4675a3a
|
[Tool] Add missing file
|
2021-01-15 14:48:19 -07:00 |